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The functionality of CMOS logic is dependent on the concept of a gate’s ability to successfully convey state based upon the voltage it receives on it’s input/s to that

produced on it’s output. The simplest mapping of input to output voltages of an inverter is known as the voltage transfer characteristic. From this, two input voltage thresholds are derived. The first is Voltage Input High (VIH), which defines the minimum voltage that the input will deterministically recognize as a valid state of ‘1’. The second is Voltage Input Low (VIL), which defines the maximum voltage that the input will

deterministically recognize as a valid state of ‘0’. Between these voltages, the combined impact of the NMOS/PMOS devices on the drain are indeterminate, and therefore the ability to deterministically convey state has been lost and the logic cannot be deemed operational. From the two input thresholds, two output levels may be derived. The Voltage Output Low (VOL) is derived as the voltage on the output when the voltage on the input is VIH. The Voltage Output High (VOH) is derived as the voltage on the output when the voltage on the input is VIL.

In order for a gate to be able to drive itself, VOH must be greater than VIH for a state of ‘1’ to be successfully conveyed from one stage to the next. The difference between VOH and VIH is known as the Noise Margin (High), NMH. VOL must also be less than VIL to successfully convey a state of ‘0’. The difference between VIL and VOL is known as the Noise Margin (Low), NML. The theoretical operation of CMOS may therefore be defined as valid when both NMH and NML are greater than zero. As the number of gates in a design increases, the likelihood of a gate failing to meet this criteria increases, and therefore the MOV increases [83].

Two primary issues are posed by operation in the subthreshold regime. The first is that as supply voltage is aggressively scaled, MOS devices stop behaving like voltage controlled current sources and start behaving in an ohmic fashion. The voltage dropped across them therefore begins to account for a greater proportionality of the rail to drain voltage, degrading the output swing of the gate. Degradation of the output levels degrades the noise margins.

The second issue is that the inherent strengths of NMOS/PMOS devices are degraded at different rates under aggressive voltage scaling. Typically in bulk planar deep submicron technology nodes, the PMOS device degrades more than the NMOS device. This results in a reduction in VOH and a corresponding degradation of the NMH. As such, aggressive voltage scaling will eventually lead to gate failure. It is therefore imperative to determine the impact of the limits of operability on device sizing.

A test bench was created to simulate these limits from the BSIM compact model. This test contains a single inverter with NMOS and PMOS devices of matched width and length, giving a 1:1 P/N sizing ratio. A supply voltage is applied, and the input voltage to the inverter swept from ground to the supply voltage to generate the voltage transfer characteristic. VIL and VIH are determined as the input voltage levels which generate first order derivatives equal to -1, a common methodological practice used in the field. VOH and VOL are then determined as the output voltages corresponding to the input voltages VIL and VIH. The noise margins NMH and NML are calculated as absolute values and also as a percentage of the supply voltage. The supply voltage is then lowered and the whole process repeated. The practical minimum operating voltage is then

determined as the point at which either NMH or NML reaches 10% of the supply voltage, again a common methodological practice in the field. Finally, the whole test bench is geometrically swept over length and width for both LVT and RVT variant s of the devices. Figure 38 shows the results.

Figure 38 shows the practical minimum operating voltage of the LVT device inverter at the TT process corner and a temperature of 25°C. The trend shows that increasing the device length and width has the effect of decreasing the minimum operating voltage. Both the drive current sweeps for the NMOS and PMOS devices showed positive current trends for length and width. For the purposes of propagation delay, gate capacitance grew faster than drive current and therefore propagation delay was minimal at around 150nm length and minimum width. For noise margin, the results suggest the relationship is somewhat more complicated. The overall result is likely a combination of many factors, including Ion/Ioff ratio, P/N optimal sizing, threshold voltage variation in response to sizing, drive current, inherent ohmic nature of the devices etc. Interestingly, large gains in minimum operating voltage can be made by upsizing slightly from minimum dimensions. The gains then swiftly diminish. For a length sized at 150nm for minimum propagation delay, a 25mV improvement in minimum operating voltage can be obtained by upsizing the width to 350nm. The lowest minimum operating voltage for the analysis was 133mV for lengths/widths greater than 950mV. The highest was 190mV, covering the whole width of the minimum length devices.

Figure 38 also shows the practical minimum operating voltage of the RVT device inverter at the TT process corner and a temperature of 25°C. This is quite different to the LVT response, with a local minimum centered on a length of 240nm and width of 300nm. Increasing beyond these values increases the minimum operating voltage. Again the response is likely an amalgamation of many factors. The lowest minimum operating voltage in the response is 109mV at the 240nm/300nm minimum focal point outlined above. The highest was 149mV at minimum length.

Several conclusions may be drawn for the above analysis. Firstly, the optimal sizing for minimum propagation delay and minimum operating voltage are not the same. A design decision between performance and yield is therefore presented to the library designer. The second trend observed is that the worst minimum operating voltage occurs at minimum length for both device variants. The standard superthreshold practice of sizing at minimum length would therefore have significant impact on yield. A third observation is that the absolute values of the RVT variant are less than the LVT variant, which is initially somewhat counterintuitive, given that the natural threshold voltage of the RVT device is higher. The likely reasoning behind this is the greater Ion/Ioff ratio of the RVT device. As outlined earlier, MOS devices begin to display ohmic behavior at aggressively scaled voltages, resulting in logical behavior analogous to ratioed logic. In the LVT

device, the off device in the inverter will leak a larger amount of current, placing a greater contention on the drain, degrading the noise margin and therefore minimum operating voltage.

3.8 Chapter Summary

This chapter performed simulations on a BSIM 4.5 compact model of the chosen technology library. Geometric sweeps were performed to measure active and leakage currents for both PMOS and NMOS devices. These were shown to be highly dependent on LVT/RVT variant and process corner due to their impact on the manifestation of the RSCE and INWE. The Ion/Ioff ratios were then calculated. All responses showed the ratio degraded towards minimum length due to the SCE. The rest of the responses were explained using the underlying physics outlined in Chapter 2.

Minimum-fingered topologies were then explored and their active and leakage currents compared to a single iso-area device. All minimum width composite devices showed some level of improvement over a single iso-area device. The absolute magnitude of this improvement was highly device dependent.

Geometric sweeps to simulate gate capacitance were then performed. Little deviation resulting from RSCE or INWE was observed, thus supplementary simulations to

determine junction capacitance were performed. The responses showed dominance of the direct correlation of gate capacitance and area.

Propagation delay was then simulated to determine the impact of the previously simulated current and capacitance metrics on device performance. This showed the optimal sizing was highly dependent on LVT/RVT variant and process corner. The INWE dominated for all lengths above the 90nm length variation cutoff.

Finally, the minimum operating voltages were simulated to determine the impact of device sizing on robustness. These showed little correlation to performance optimal sizing.