A 8-10Gbps 4-PAM Transmitter
actively terminated with Pre-Emphasis Design
By
Jes´
us Alonzo Rodr´ıguez Ortiz
Electronics Engineer, UABC
A Dissertation submitted in partial fulfillment
of the requirements for the degree of:
MASTER OF SCIENCE
WITH MAJOR ON ELECTRONICS
at the
National Institute of Astrophysics, Optics
and Electronics
July 2016
Tonantzintla, Puebla
Advisor:
PhD. Guillermo Espinosa Flores Verdad
Principal Research Scientist
Electronics Department
INAOE
c
INAOE 2016
The author hereby grants to INAOE permission to reproduce
and to distribute copies of this Thesis document in whole or in part.
A 8-10Gbps 4 PAM Transmitter actively
terminated with Pre-Emphasis Design
Masters Thesis
By:
Jesus Alonzo Rodriguez Ortiz
Advisor:
PhD. Guillermo Espinosa Flores Verdad
National Institute of Astrophysics, Optics and Electronics Electronics Coordination
I
To my wife Stephany, my mother Maritrini, my tia Lupita and especially to my
Acknowledgements
I would like to thank to:
God and all of his blessings.
INAOE, for all the tools provided in order to conclude the master’s program, and to CONACyT for the financial support provided trough the master’s scholarship number 334284.
My wife Stephey, for your love and patience, for all the laughs and good times, for all the kind words that you said to me when I felt defeated and mostly for all of your support trough this stage of our lives which filled me with confidence to keep moving forward to a better future together. I love you.
My abuelita Chuy, for love me as one of your sons, for all the life lessons on how to become a better man that you gave me, for all the histories that you told me, for all the good memories, in summary for always being there for me with a big smile and your messy hair. I miss you.
My mother Maritrini, for all the lessons that you made me learn trough my life, your unconditional love and support made scary decisions easier to make, thanks for all the times that you were brave just to give me confidence and for always encourage me no matter what. To my second mother, my tia Lupita for always looking after me, for your advices, for taking good care of me and always wish me well even if we were apart.
Extensive family, my aunts Soco, Rosa, Conchita, Magui, Tere, Juanita, my uncle Diego, my sister Ale, my cousins and all the rest of the family, for all your support and teachings that I learned from every one each of you, it’s a blessing to have you all.
My advisors Guillermo Espinosa Flores Verdad and Miguel Angel Garcia Andra-de, for your guidance and mentorship trough different subjects, from education to
personal matters, thanks for always having your door open for me. I appreciated.
The jury Maria Teresa Sanz, Antonio Carrillo and Esteban Tlelo for taken the time to reviewing this thesis and provide observations and comments to enrich this document. Thank you for your time.
My friends Javier, Zapata, Quintas, Ochoa, Rafa and others, for your friends-hip and all the laughs that we shared through the master’s program, you guys are awesome.
Abstract
In the last decades an exponential growth in data communications has created the need to design transmission and reception system of high performance, high speed and low power consumption. This work is focused on the design on a 8-10Gbps 4 PAM transmitter actively terminated and a Pre-Emphasis circuit as well, in CMOS technology of 0.18µm to drive a 12in FR4 transmission line.
In this work, 3 proposals of 4 PAM transmitter were made and compared, one with a passive resistor and the others using NMOS transistors as termination de-vices. In all the proposals, the main core circuit was changed from the conventional transmitter to the use of 6 transistors and a current source in order to avoid mismatch with any additional current source. In the latest proposal, a transistor set array was introduced to compensate the variations of the resistance due to the output voltage node; such resistance value has to be kept at 50Ω for the characteristic impedance of the transmission line.
Also, the losses of a 12in FR4 transmission line including package models was characterized, in order to obtain the ideal values of the amount of current and the time of injection of such current for the Pre-Emphasis circuit, such circuit is based on 6 transistors that will be ON depending on the data transition, by using this additional circuit the Eye Diagram at the receiver can be improved at a low power consumption.
Finally, the whole system was simulated using HSPICE Software, and the results showed that the relation between power consumption and data rate was 1.22pJ/b at 10Gbps, which positions this work as one of the lowest power consume per transmitter bit among the State of the Art.
Resumen
El crecimiento exponencial de la comunicaci´on de datos ha creado la necesidad de dise˜nar sistemas de transmisi´on y recepci´on de alto rendimiento y bajo consumo de potencia. Este trabajo est´a enfocado en el dise˜no de un transmisor 4-PAM de 8-10Gbps con terminaci´on activa y un circuito de Pre-´Enfasis, en tecnolog´ıa CMOS de 180nm para usarse junto con una l´ınea de transmisi´on de FR4 de 12 pulgadas.
En este trabajo, 3 propuestas de transmisores 4-PAM fueron hechas y comparadas, una de ellas con un resistor pasivo y las dem´as usando transistores NMOS como dis-positivos de terminaci´on. En todas las propuestas, el n´ucleo principal del transmisor 4-PAM convencional fue cambiado para usar 6 transistores y una fuente de corriente para evitar el desapareamiento con cualquier fuente de corriente adicional. En la ´ ulti-ma propuesta, una estructura de transistores usada como dispositivo de terminaci´on fue presentada para compensar las variaciones de su resistencia equivalente, dadas por las variaciones del voltaje del nodo de salida, la cual tiene que mantenerse en 50Ω por la impedancia caracter´ıstica de la l´ınea de transmision.
Tambi´en, se hizo una caracterizaci´on de las p´erdidas debidas a una l´ınea de trans-misi´on de FR4 de 12 pulgadas en conjunto con el modelo del empaque para obtener los valores id´oneos de la corriente y el tiempo de inyecci´on de dicha corriente para el circuito de Pre-´Enfasis, el cual est´a conformado por 6 transistores que dependiendo de la transici´on de los datos estar´an encendidos o no, con este circuito el Diagrama de Ojo de los datos puede ser mejorado a bajo costo de potencia consumida.
Finalmente, el sistema completo fue simulado y los resultados mostraron que la relaci´on entre consumo de potencia y bit transmitido fue de 1.22pJ/b a 10Gbps, lo cual posiciona este trabajo entre uno de los que menor potencia consume para transmitir un bit entre el estado del arte.
Contents
Abstract V
Resumen VII
List of Figures XI
List of Tables XV
1. Introduction 1
1.1. A communication system, an electronic overview . . . 1
1.2. Signal Integrity . . . 3
1.2.1. Digital Signals Non Idealities . . . 3
1.2.2. Eye Diagram . . . 5
1.3. Transmission Systems Theory . . . 6
1.3.1. Transmission Line Basics . . . 7
1.3.2. Transmitters and Protocols . . . 8
1.3.3. Pre-emphasis and Equalization . . . 10
1.3.4. Voltage and Current Operation Modes . . . 11
1.3.5. Codes . . . 11
1.4. Objective and Thesis Organization . . . 12
2. 4-PAM Transmitters and Pre-Emphasis Theory 15 2.1. 4-PAM Transmitters . . . 15
2.1.1. 4-PAM Transmitters speed effects to the Eye Diagram . . . . 15
2.1.2. Ideal current mode 4-PAM transmitter model . . . 16
2.1.3. Conventional current mode 4-PAM transmitter model . . . 17
Observations . . . 22
2.2. Pre-Emphasis Circuits . . . 24
2.2.1. Ideal current mode Pre-Emphasis model . . . 24
2.2.2. State of the Art. . . 26
2.3. Comparative between works . . . 28
3. 4-PAM Transmitter Design 31 3.1. Proposal 1 . . . 31
3.1.1. Description and Analysis . . . 31
3.1.2. Simulation Results . . . 34
3.2. Proposal 2 . . . 39
3.2.1. Description and Analysis . . . 39
3.2.2. Simulations Results . . . 41
3.3. Proposal 3 . . . 49
3.3.1. Description and Analysis . . . 49
3.3.2. Simulation Results . . . 52
3.4. Comparative between proposals . . . 58
3.4.1. Power consumption . . . 58
3.4.2. Transmitter Eye Diagram . . . 59
3.4.3. Resistance Variations . . . 62
3.5. Conclusions . . . 64
4. Pre-Emphasis Circuit Design 65 4.1. Transmission Line Characterization . . . 65
4.2. Proposed Pre-Emphasis Circuit . . . 77
4.3. Conclusions . . . 80
5. 4-PAM transmitter with Pre-Emphasis Results 81 5.1. Simulation Setup . . . 81
5.2. Simulation Results . . . 82
6. Conclusions and Future Work 91 6.1. Future Work . . . 92
List of Figures
1.1. Simple Communication System. . . 2
1.2. Deviations due to a) Level degradation and Jitter, b) Intersymbol In-terference. . . 4
1.3. Ideal Eye Diagram of a 2 level Digital Signal. . . 5
1.4. Eye diagram of a 2 level digital signal a) Ideal, b) Real. . . 6
1.5. Transmission Line equivalent model of infinitesimal length z. . . 7
1.6. Pulse Amplitude Modulations a) 2 level , b) 4 Level. . . 9
1.7. 8 Levels Pulse Amplitude Modulation. . . 9
1.8. Recovering signal integrity through a) Equalization, b) Pre-Emphasis. 10 2.1. Transmitter Eye Diagram with transition times, a) Not enough, b) Just enough, c) More than enough, to reach desired level. . . 16
2.2. 4-PAM current mode transmitter model. . . 17
2.3. Conventional 4-PAM transmitter. . . 18
2.4. 4-PAM transmitters actively terminated. [1] . . . 19
2.5. Simulation diagram.[1] . . . 21
2.6. Back impedance frequency response. [1] . . . 21
2.7. Eye diagram at, a) the transmitter at 8Gbps, b) the receiver at 8Gbps, c) the receiver at 10Gbps. [1] . . . 22
2.8. Normalized Montecarlo Width Variations. . . 23
2.9. Transmitter Output Current Eye Diagram, a) Nominal, b) Current Sources Mismatch Montecarlo Iterations. . . 23
2.10. Ideal Pre-Emphasis Model. . . 25
2.11. Ideal Pre-Emphasis Model modified to 4-PAM. . . 25
2.12. Possible Data transitions. . . 26
2.14. Pre-Emphasis Circuit.[3] . . . 27
3.1. 4-PAM Transmitter proposal 1. . . 32
3.2. Input Data Voltage Sources. . . 34
3.3. Circuit Bias Current. . . 35
3.4. Biasing Current Source Vds. . . 35
3.5. Current from Core transistors M0−2. . . 36
3.6. Current from Core transistors Overlapped. . . 37
3.7. Positive Branch’s Total current. . . 37
3.8. Current Divider from positive branch. . . 38
3.9. Current Divider from negative branch. . . 38
3.10. Transmitter Output Current. . . 38
3.11. 4-PAM transmitter proposal 2. . . 39
3.12. Auxiliary Biasing Circuit. . . 41
3.13. Circuit Bias Current. . . 42
3.14. Biasing Current Source Vds. . . 43
3.15. Current from Core transistors. . . 44
3.16. Current from Core transistors overlapped. . . 44
3.17. Positive Branch’s Total current. . . 45
3.18. Node X Voltage. . . 45
3.19. Voltage Vout+. . . 46
3.20. Termination Transistors Vgs. . . 46
3.21.MT+ Current. . . 47
3.22. Resistance of MT−. . . 47
3.23. Resistance of the Termination Transistor MT1. . . 48
3.24. Transmitter Output Current. . . 48
3.25. 4-PAM transmitter proposal 3. . . 49
3.26. NMOS transistor Ids vs Vds curve . . . 50
3.27. Auxiliary Biasing Circuit. . . 51
3.28. Circuit Bias Current. . . 53
3.29. Biasing Current Source Vds. . . 53
3.30. Current from Core transistors. . . 54
3.31. Current from Core transistors overlapped. . . 54
LIST OF FIGURES XIII
3.33. Termination transistorsM1,3 Vgs. . . 55
3.34. Termination transistorsM2,4 Vgs. . . 56
3.35. Equivalent resistance fromRds1//Rds3 and Rds2//Rds4. . . 56
3.36. Total Resistance of positive and negative branch. . . 57
3.37. Current from Correction transistors. . . 57
3.38. Transmitter Output Currents. . . 58
3.39. Transmitter Output Eye Diagram Proposal 1 at 8Gbps. . . 60
3.40. Transmitter Output Eye Diagram Proposal 2 at 8Gbps. . . 60
3.41. Transmitter Output Eye Diagram Proposal 3 at 8Gbps. . . 61
3.42. Proposal 2 Equivalent Resistance Histogram. . . 63
3.43. Proposal 3 Equivalent Resistance Histogram. . . 63
4.1. Pre-Emphasis Modeling. . . 66
4.2. Pre-Emphasis Ideal Model. . . 66
4.3. Transmitter Output Eye Diagram. . . 68
4.4. Characterization Circuit. . . 69
4.5. Transmission Line with package parasitics frequency response. . . 70
4.6. Pre-Emphasis Modeling no Pre-Emphasis. . . 70
4.7. Pre-Emphasis Modeling Case 1. . . 71
4.8. Pre-Emphasis Modeling Case 2. . . 71
4.9. Pre-Emphasis Modeling Case 3. . . 72
4.10. Pre-Emphasis Modeling Case 4. . . 73
4.11. Pre-Emphasis Modeling Case 5. . . 73
4.12. Pre-Emphasis Modeling Case 6. . . 74
4.13. Pre-Emphasis Modeling Case 7. . . 74
4.14. Pre-Emphasis Modeling Case 8. . . 75
4.15. Pre-Emphasis Modeling Case 9. . . 75
4.16. Time Delay. . . 76
4.17. Percentage of Vertical Opening from Cases 1-11. . . 77
4.18. Percentage of Horizontal Opening from Cases 1-11. . . 77
4.19. Pre-Emphasis Circuit Proposal. . . 78
4.20. Pre-Emphasis Output Current. . . 79
4.21. Correction Current from Pre-Emphasis Circuit. . . 79
5.2. Differential Voltage Eye Diagram at 8Gbps. . . 82
5.3. Differential Voltage Eye Diagram at 10Gbps. . . 83
5.4. System Equivalent Resistance Histogram at 8Gbps data rate. . . 84
5.5. System Equivalent Resistance Histogram at 10Gbps data rate. . . 85
5.6. Differential Voltage Eye Diagram under process and temperature va-riations at 8Gbps, a) without Pre-Emphasis, b) with Pre-Emphasis. . 86
5.7. Differential Voltage Eye Diagram under Process and Temperature va-riations at 10Gbps, a) without Pre-Emphasis, b) with Pre-Emphasis. 87 5.8. Equivalent Resistance under Process and Temperature variations at 8Gbps. . . 88
List of Tables
1.1. Equivalence Between Codes . . . 12
2.1. Iout dependency on data input. . . 17
2.2. Comparison between Conventional 4-PAM transmitter and [1]. . . 20
2.3. Performance Summary of [1]. . . 22
2.4. State of the Art. . . 29
3.1. Currents in function of Thermometer input data. . . 33
3.2. Device’s values and dimensions of Proposal 1. . . 33
3.3. Device’s values and dimensions of Proposal 2. . . 42
3.4. ON signals of Correction Transistors. . . 51
3.5. Device’s values and dimensions of Proposal 3. . . 52
3.6. Proposals Eye characteristics. . . 61
3.7. Proposals Level positioning. . . 62
4.1. Current Source dependence on data transition . . . 67
4.2. Pre-Emphasis modeling cases. . . 69
4.3. UMC standard MOS 0.18µm technology values. . . 78
4.4. Addition/Subtraction dependency of PAM level change. . . 80
5.1. System Eye characteristics Summary. . . 84
5.2. Systems Levels Summary. . . 84
5.3. System PT Eye characteristics Summary. . . 87
Chapter 1
Introduction
In the last decades an exponential growth in data communications has created the need to design transmission and reception systems of high performance, high speed and low power consumption. Nowadays, this has been accomplished thanks to the shrinking of the CMOS transistor channel length, allowing communications transmission speeds to go well above the Giga bit per second (Gbps) data rate, and as a direct result high speed Internet, 5G mobile networks and powerful microprocessors are a reality. However, the impulse to make more efficient the use of Bandwidth and Power has led to rediscover the communications transmitters and propose newer systems that optimize all the mentioned above and because of this, there are several opportunity areas to work with; for example prevent/correct errors, reduce power consumption and improve transmission data rate, all of this using low cost materials and devices.
The content of this chapter can be described as follows: a description of a com-munication system, signal integrity theory, basic transmission line theory and digital communication modulation schemes. Also a comparison between current mode versus voltage mode is presented and finally the objective of this thesis is exposed.
1.1.
A communication system, an electronic
over-view
In Fig. 1.1, an electronic communication system is shown, although this diagram can be used in several areas; particularly in electronics refers to the system that delivers the processed signal to a different receiver block or blocks. It is grossly divided in four main parts: message, transmitter, transmission medium and receiver [4].
Figure 1.1: Simple Communication System.
Message: Is the signal with the information that is being sent, as any signal this can be analog or digital, the latter is preferred for showing some advantages like it robustness to noise and distortion. [5]
Transmitter: It has the duty to adapt the message to a pre-defined communi-cation protocol and medium, this sub-system can be in current mode or voltage mode, the main differences will be explained later in this section.
Medium: This element will define the type of communication system to use, which basically are: fiber, copper and wireless the use of any of them will be determined by the application, distance, data rate and cost. Optic fiber is often used to cover long distances (>1 km) and high data rates (>100 Gbps), on the other hand, copper is effective in medium distance (<1 km) and medium-high data rates (up to a few Gbps) and finally air is used in medium distances (1km) and medium data rates (up to ∼100 Mbps). [6]
Receiver: Is the responsible to recover the message coming from the medium and deliver it to the user as it was originally sent. As well as the transmitter, it can be implemented in current or voltage mode.
All the mentioned above are fundamental blocks for a communication system, ideally the message at the far end of the system must present no errors, but in reality this might be not possible for the performance of the transmitter and receiver, and the characteristics of the medium. There are losses in all the blocks mentioned before, and the designer must compensate those losses and deliver a message identical to the one sent.
1.2 Signal Integrity 3
1.2.
Signal Integrity
As told before, losses are expected in any real communication system and it is necessary to take them into account to evaluate the quality of the signal. The term of signal integrity, generally is defined as any deviation from ideal waveform [7], and is strongly related to noise (undesired signal that is added to the signal under test and affects the performance of the system).
In analog signals, the signal integrity is given by the relation between the signal and the noise power which is called Signal to Noise Ratio (SN R) as shown in (1.2.1), ideally the SN R must be infinite, that will imply that the noise power is 0.
SN R= Psignal
Pnoise
(1.2.1)
BER= ErroneousBitsReceived
T otalBitsSent (1.2.2)
In digital signals, the Bit Error Rate (BER) evaluates the relation between the erroneous received bits and the total sent bits of the digital signal under test [6], as seen in equation (1.2.2). At contrary, that SN R, BER ideally must be equal to 0, this would mean that all the bits are received correctly.
Both of them are important, however it is necessary to define some additional parameters to evaluate and have a complete overview of the signal quality. In this work only digital signals will be considered.
1.2.1.
Digital Signals Non Idealities
The deviation of a digital signal from its ideal, can be viewed in two principal aspects: Amplitude and Timing.
First, lets consider a binary digital signal as the one shown in Fig. 1.2 a, this will have 2 digital levels (0 level and 1 level) which correspond to a value in voltage (or current) in amplitude, when the signal did not reach or surpassed the corresponding level, it is said that have a deviation in amplitude ∆a, more specific the signal presents level degradation.
Secondly, when the signal makes any transition, this has to coincide perfectly with the transition of the ideal signal, if the signal goes before or after the ideal transition
Figure 1.2: Deviations due to a) Level degradation and Jitter, b) Intersymbol Interference.
point, the signal will have a time deviation ∆t (Fig. 1.2 a, this is called timing jitter, or simply jitter. When these deviations are due to physical properties of the devices, they are intrinsic (or random) deviations, and when the deviations are design related they are called extrinsic (or systematic) deviations, and they may be eliminated using adequate design techniques.
Nevertheless, there are some non idealities that are not covered by amplitude or timing deviations alone, this is the case for the intersymbol interference (ISI) and crosstalk that may cause amplitude and/or timing deviations, the first (ISI) is dependent on the medium and the data being sent. Considering a binary data stream, this can take values of digital levels 0 and 1, and also any level can keep its amplitude for some time, supposing that a high level is kept in a copper medium, this will charge the parasitic capacitances of the copper and will add some additional discharge time, hence will require a longer time to settle when a transition is made and may lead to an incorrect level (Fig. 1.2 b), this will cause a time and amplitude deviation that affects the signal integrity, it is called intersymbol because the data sent in a specific interval (symbol) affects the following data.
On the other hand, the crosstalk it refers to the situation where energy from a signal on one line is transferred to a neighboring line by electromagnetic means [8], in other words due to a capacitive and inductive coupling between transmission lines the signal from one line may interfere with another, this may cause amplitude and timing deviations.
1.2 Signal Integrity 5
1.2.2.
Eye Diagram
The non idealities discussed in the last section are better appreciated if they are seen in a graph, therefore a visual tool is needed to evaluate the sent/received digital signal integrity; the Eye Diagram is a useful tool that fulfills that purpose.
As seen in Fig. 1.3, the Eye Diagram is a graph that is formed with the superimpo-sition of all the possible transuperimpo-sitions of the signal under test and with this, is possible to see the amplitude and timing behavior of the signal. There are some parameters of interest:
Figure 1.3: Ideal Eye Diagram of a 2 level Digital Signal.
Crossing Time: It is defined as the ideal point in time where (when there is a transition) the signal is at half amplitude.
Unit Interval: Is the time where a single symbol is.
Crossing Amplitude: The point where is the half amplitude between levels.
Levels: The amplitude levels of the signal, will depend on how many levels the signal has.
The vertical axis is amplitude and its range is between the amplitude levels, on the other hand the horizontal axis is time and generally in its range are two unit intervals and often one of them is centered for convenience.
Figure 1.4: Eye diagram of a 2 level digital signal a) Ideal, b) Real.
As it is shown in Fig 1.4 a, ideally the system must not present any amplitude level degradation and none jitter as well, this would imply that the signal is being sent/receive with the right upper and lower amplitude levels, in this case the vertical (amplitude between levels) and horizontal opening (time between transitions at half amplitude) of the Eye Diagram are said to be maximum and the eye have a hexagon shape, having a maximum eye opening will imply that all the bits sent are received correctly, and therefore the BER will be ideally 0. However, in real systems level degradation and jitter are present, and it is reflected on the Eye Diagram vertical and horizontal openings, and in overall shows an oval shape eye in the graph as seen in Fig 1.4 b. In this case the BER will be degraded, we want to keep this value as low as possible, a BER at or lower that 10−12can be an acceptable level on communications
systems [6].
1.3.
Transmission Systems Theory
When an electronic transmission system is going to be designed, certain specifi-cations has to be made beforehand, such as medium characteristics, communication protocol and decide if a voltage or current mode circuit is going to be used. These
1.3 Transmission Systems Theory 7 decisions are important because they will define the circuit implementation guidelines.
1.3.1.
Transmission Line Basics
At very high frequencies the conventional modeling of a conductor is inaccurate to model some effects and transmission line theory is used to correct this, basically the conductor (now referred as transmission line) is treated as a two port network of distributed elements, that makes it act as a low pass filter, which in copper can be coaxial cables, micro-strip, waveguides etc.
Figure 1.5: Transmission Line equivalent model of infinitesimal length z.
As seen in Fig. 1.5, the transmission line can be modeled by distributed elements along the line itself (over an infinitesimal segment), those elements are resistances, capacitors and inductors: the resistance is related to the amplitude losses (because the line is not a perfect conductor), the capacitance is due to the separation of two conductor plates by a dielectric (which is the case of coaxial cable and microstrip lines), and the inductors are present because of the AC current that flows through the line. All these elements are intrinsic material and its effects will affect the signal integrity. [9]
Another interesting properties that a designer must consider are the length and the characteristic impedance of the line. The length is important because it will affect directly on the losses of the signal, the longer the line the greater the losses, naturally the losses vary between different types of transmission lines and its uses depends on the application. The characteristic impedance is a property from copper transmission lines, that allows the correct coupling at the near end and the far end of the line, if the termination of the transmitter circuit is not matched with the line characteristic impedance, part of the signal will be reflected to the transmission circuit and perhaps damage it; on the other hand at the far end of the line, if the load is not matched
with the characteristic impedance the maximum transfer energy theorem will not be kept.
In the industry, there are standards for transmission lines, the material could be FR-4 for it cheapness, the characteristic impedance is 50 ohms and the length varies depending of the application but generally are 7.5 inches or 12 inches, those specifications will be the reference of the transmission line used in this work.
1.3.2.
Transmitters and Protocols
There are different types of transmitters, the selection of any of them will depend on the signal (digital or analog) and the modulation scheme. There are many kinds of modulation, but amplitude and frequency are mainly used in electronic communi-cations. In both of them, a code or protocol is needed to standardize the signal and make it compatible to different receivers.
One of the most used amplitude modulation schemes is the n-PAM (Pulse Am-plitude Modulation), where n is the amAm-plitude level number in the modulated signal. The number of levels will determine the level spacing of the signal swing of the trans-mitter, and hence the number of eyes in the eye diagrams, this can be seen in Eq. (1.3.1) [10]. As the number of level increases, the level spacing decreases.
LevelSpacing = T ransmitterSwing
n−1 (1.3.1)
However, as the number of levels goes up, a higher number of bits can be trans-mitted at a single symbol rate, this is expressed by Eq. (1.3.2), this implies that n
can only that values power of 2 for efficiency.
BitsT oT ransmit=log2(n) (1.3.2)
The simplest n-PAM scheme is the 2-PAM, which is shown in Fig. 1.6 a, its 2 digital levels made it compatible with digital circuitry and eased the full implementation in systems, however as higher data rates were demanded, 2-PAM became insufficient.
The 4-PAM circuits solve the limitations of 2-PAM, as shown in Fig. 1.6 b. The 4-PAM is capable to sent the double of bits in the same unit interval, this is done by forming 4 signal levels (00, 01, 10 and 11) and in analog signal 0, 1/3, 2/3 and 1 times the maximum amplitude of the signal. This implies a data rate doubling with the same bandwidth. Also using this scheme, ISI is diminished because the data
1.3 Transmission Systems Theory 9 transition are more often and crosstalk is also diminished using a differential 4 level signal.
Figure 1.6: Pulse Amplitude Modulations a) 2 level , b) 4 Level.
Figure 1.7: 8 Levels Pulse Amplitude Modulation.
Although its possible to use 8-PAM (Fig. 1.7) or higher, this is often not convenient because the transmitter/receiver will require a higher resolution to process correctly the data, also with smaller level spacings the signal sent will be suitable to noise and distortion effecting the data sent, no forgetting that level amplitude degradation will have a higher impact in the vertical eye opening.
For all the reasons mention above a 4-PAM scheme circuit is preferred over the others and is even a standard protocol in the industry, its advantages can be exploited to make more efficient the bandwidth at low cost, which is why a 4-PAM scheme will be used in this work.
1.3.3.
Pre-emphasis and Equalization
It is common that systems transmitting at a Gbps data rates have a poor data eye vertical/horizontal opening which makes the system error suitable and therefore have a non-acceptable BER. This created the need of a system to recover the signal integrity; there are two main ways to achieve that, one on the far end of the transmis-sion line and other on the near end which are called Equalization and Pre-Emphasis respectively.
Figure 1.8: Recovering signal integrity through a) Equalization, b) Pre-Emphasis.
Equalization: As seen in Fig. 1.8 a, the sent signal is received from the medium, the amplitude levels and the transition point are evaluated and compared from its ideal values, and with this information the equalization system attempts to correct the signal to the desired values, this will open the received data eyes vertically and horizontally. Generally, the equalization system uses feedback and dynamic correction ([11], [12]), and its active until a desired eye opening is reached; often complicated circuitry and complex algorithms are used to achieve this.
1.3 Transmission Systems Theory 11
Pre-Emphasis: Using a previous characterization or modeling of the transmis-sion line, the signal to be sent is modified in order to compensate the losses in the medium, by doing this, a modified sent signal will arrive at the far end with better vertical and horizontal eye opening as shown in Fig. 1.8 b. This kind of systems depends on the transitions of the message that is being sent, this task is performed for some kind of mixed analog/digital system.
They are two different techniques to achieve the same purpose and both of them shows pros and cons. In the case of equalization, the system can correct level degrada-tion and random jitter. In contrast to Pre-Emphasis that only can compensate level degradation and systematic jitter, although is still desirable for its implementation simplicity. Bottom line, it will depend on the system requirements and the designer decides which one is more suitable for the system, however there is no restrains to use both systems. In this work the idea is to explore a simple solution to maintain a low power consumption, a pre-emphasis technique will be used.
1.3.4.
Voltage and Current Operation Modes
There are two main operation modes in electronics, in voltage or current. The voltage mode is used very often in a great variety of circuits and for some, is preferred over the current mode, however it presents a few drawbacks in modern technology where the threshold voltage has not been reduced at the same scale as the supply voltage, this limits the number of transistors that can be connected in cascade and the dynamic range as well. In current mode, as the operation is not limited by the nodal voltage swing, circuits in this mode are suitable to work under low voltage conditions and are robust to variations of the supply voltage, also if a transmitter is used for close range communications, current outputs can provide faster communications than voltage outputs [13], this qualities makes them desirable for a number of applications from communications to analog signal processing [14].
1.3.5.
Codes
The input/output coding scheme may vary between applications, the most com-mon representation of decimal numbers is the binary coded decimal (BCD) [15], it uses a 4-bit binary code to represent a decimal number and is extensively used in digital systems.
Table 1.1: Equivalence Between Codes
Decimal BCD
D3D2D1D0 Thermomether
Inverse
Thermomether Bubble
0 0000 0 1 000000000
1 0001 01 10 000000001
2 0010 011 100 000000010
3 0011 0111 1000 000000100
4 0100 01111 10000 000001000
5 0101 011111 100000 000010000
6 0110 0111111 1000000 000100000
7 0111 01111111 10000000 001000000
8 1000 011111111 100000000 010000000
9 1001 0111111111 1000000000 100000000
Secondly, the thermometer code is also used, in such code for an increasing bi-nary (or decimal) number, the number of “1”s is also increasing, in other words the number of “1”s corresponds to the decimal number, on the other hand, the inverse thermometer code the number of “0”s corresponds to the decimal number, by using a simple gate function the conversion between BCD to thermometer and backwards can be obtained in a easy manner as exposed in [16].
And finally, in the bubble code the position of the “1” between a set of “0”s indicates the corresponding number. The equivalence between codes is shown in Table 1.1, as it can be seen if the decimal number “3” is required in BCD its equivalent to 11 (D1D0), in thermometer code is equivalent 0111 (there are 3 numbers “1”),
similarly in inverse thermometer will be 1000 (there are 3 numbers “0”) and finally in bubble code will be 01000 ( the 1 is in the third position from right to left).
1.4.
Objective and Thesis Organization
The objective of this thesis is to design a 8-10Gbps current mode 4-PAM transmit-ter actively transmit-terminated and a Pre-Emphasis system for driving a 50 ohm transmission line of FR4 of 12 inches using UMC CMOS technology of 0.18µm.
The thesis organization will be as follows: in chapter 2, a review of the 4-PAM transmitters and Pre-Emphasis circuits is made, that includes establishing ideal mo-dels and an overview of the State of the Art for both circuits. Then in chapter 3, a
1.4 Objective and Thesis Organization 13 comparison between 4-PAM transmitters of 3 different proposals was made, in this chapter the analysis and simulations are presented and also the decision of which one was the best among the proposals. A similar analysis was made in chapter 4 with the Pre-Emphasis circuit proposed, also its simulations and discussion were presented. In chapter 5, the simulation results of the system conformed by the chosen 4-PAM transmitter proposal in chapter 3 and the Pre-Emphasis circuit are presented. And finally, in chapter 6 the conclusions and future work are presented.
Chapter 2
4-PAM Transmitters and
Pre-Emphasis Theory
In this chapter, ideal models of 4-PAM transmitters and Pre-Emphasis will be established, as well as a conventional 4-PAM transmitter circuit and a review of the State of the Art of both circuits; this is necessary because it is important to know where the opportunity areas are to work with, and will give a general overview of the works published in the matter.
2.1.
4-PAM Transmitters
2.1.1.
4-PAM Transmitters speed effects to the Eye Diagram
As exposed before, there are advantages of implementing a 4-PAM transmitter in current mode, one of the most important is transition speed. The transmitter transition time will determine the data rate to transmit, and also will affect greatly the data eye opening. To make this point clearer, let’s consider 3, 4-PAM transmitters working at an arbitrary data rate with different transition times where 3 general cases can be observed:
Transition time at some transitions is not enough to reach to the desire amplitude level: This will close the data eyes greatly as shown in Fig. 2.1 a), and the BER will have and unacceptable value. In this case the transmitter is working beyond its operation limit and data are compromised.
Transition time is just enough to reach to the desired level: In this case the transmitter is at or reaching its operation speed limit. Even though the
data eyes do have an opening (Fig. 2.1 b)), the effectiveness of this transmitter will be determined by theBER.
Transmitter transition time is more than enough to reach the desired level: Given that the transition is abrupt, it will take lesser time to settle and hence, the data eyes will be greatly open (Fig. 2.1 c)) having a very low BER (which is the optimum). Since this transmitter may be working at a low data rate, increasing it could be considered.
Figure 2.1: Transmitter Eye Diagram with transition times, a) Not enough, b) Just enough, c) More than enough, to reach desired level.
2.1.2.
Ideal current mode 4-PAM transmitter model
As exposed before, there are advantages of using the 4-PAM modulation sche-me and implesche-menting the transmitter in current mode, therefore it’s important to establish a 4-PAM transmitter model in current mode.
A 4-PAM current mode transmitter can be ideally modeled by 4 current sources, a termination resistor and 4 switches, as seen in Fig. 2.2 in a dashed box. These switches control the magnitude of Iout, and only one switch can be closed at a time and they
are controlled by the data to be sent, for example, if the binary data is 00 the switch
S0 will be closed and switches S1 toS3 will be open, similarly 01 controls switch S1,
2.1 4-PAM Transmitters 17
Figure 2.2: 4-PAM current mode transmitter model.
value of the line characteristic impedance, this will ensure the correct matching with the line at the near end and kept the maximum energy transfer theorem at the far end.
Using a resistor to terminate the transmitter presents an inconvenient, since the resistorsRT and RL are matched to the transmission line, the current will be divided
on the output node, this will imply that only half of the current will reach to the load, and the other half will be dissipated in the termination resistorRT. The Table
2.1 summarizes the switches controls using a BCD to Bubble code decoder, and also takes into account the current divider at the output.
Table 2.1:Iout dependency on data input.
Data\Switch S0 S1 S2 S3 Iout
00 closed open open open 0 01 open closed open open 1/6∗I
10 open open closed open 1/3∗I
11 open open open closed 1/2∗I
2.1.3.
Conventional current mode 4-PAM transmitter model
A conventional 4-PAM transmitter is shown in Fig. 2.3, it is constituted by two differential pairs driven by current sources of magnitude I and 2I, and also 2 termi-nation resistors. Since the gates of the NMOS transistors are controlled by the data binary bits and their respective negatives to send (D0+, D0−, D1+ and D1−), they
are responsible to manage the current at the outputs, the current Iout+ will be the
Iout− will be determined by the addition of M0− and M1− currents. For example, if
the binary data to send is 00 (D1D0, the transistorsM0+ andM1+ will be turned off
(cut off region), making Iout+ = 0 and Iout− = 12 ∗3I (due to the current divider at
the output). The signal swing in the output nodes will be determined by the current flowing through the resistor R, Vout = Vdd −R∗IR , this implies that if a twice as
large signal swing is needed it will require to double up the current from the sources
I and 2I, and hence the global power consumption will go up.
Figure 2.3: Conventional 4-PAM transmitter.
2.1.4.
State of the Art
A New Power Efficient Current-Mode 4-PAM Transmitter Interface for Off-Chip Interconnect [1] paper review This paper presented by Vijaya San-kara shows a power efficient 4-PAM transmitter and introduces the use of a NMOS transistor as a termination device, this circuit is presented in Fig. 2.4, and 2 stages (Main Driver and Replica Stage) can be seen: the first stage is based by transistors
M0, M3, M4 and M6 and current sources of values Itail and 2Itail, and the second
stage is based by transistors M1 andM5 as well as two resistors of valuekR0 and two
current sources of value Itail/k and 2Itail/k, their purposes will be explained next:
2.1 4-PAM Transmitters 19
Figure 2.4: 4-PAM transmitters actively terminated. [1]
line, in other words, this stage will drive directly the transmission line. Its fun-ction is very similar to the conventional 4-PAM transmitter, the sum of the cu-rrent will be added in an Output node.This transmitter presents an advantage, since the termination devices of this circuit are NMOS transistors (M3, M6)and
are biased such that for the outbound signal, the load devices are open circuit. So, the main driver signal current( 3Itail) completely flows onto the line [1], in
other words the nodes X/Y and nodesOut+/Out− varies in a way that allows
a Vgs3,6 = 0 in small signal, having a quiescent current in these devices allowing
a proper dimensioning to match the impedance of the device (Zback) with the
characteristic impedance of the line, which will ensure its correct coupling, this is done by using Eq. (2.1.1).
Zback(0) =
1
gm3+gm6+gmb3+gmb6
(2.1.1)
Replica Stage: This stage ensures the signal swing matching between nodes
but transistorsM3,6 were replaced with resistors and current sources have been
scaled (k) for the next reason: Considering that the voltage of the output nodes of the main driver are given byIout∗Rout, where Iout is the output current and
Rout is the output resistance of the main driver, this voltage has to be replicated
in nodesX/Y. This is done by scaling the resistork timesRo and dividing the
current sources for the same k factor , with this the voltage in nodes X/Y will be Iout/k ∗kRout = Iout ∗Rout, the same as the output voltages of the main
driver and hence the Vgs in small signal will be 0 allowing a quiescent current
through the termination device.
Power Dissipation and Signal Swing As mentioned before, this 4-PAM trans-mitter presents advantages in power efficiency, even though it uses extra power for the replica stage (as seen in Eq. (2.1.2)), it is capable of delivering the double signal output current, comparing it to the conventional 4-PAM transmitter, where it needs the double of power to draw the same signal.
Pactive = (3Itail+
3Itail
k )Vdd (2.1.2)
The power savings are function of thek factor, [1] usedk = 4 in order to maintain a balance between operation speed and power consumption, the power savings are 37.5 % compared to the conventional 4-PAM transmitter with an ideal top of 50 %, as seen in equation 2.1.3 . Finally, the Table 2.2 exposes a brief comparison between the conventional 4-PAM transmitter and the one presented in the paper.
Psavings=
1 2(1−
1
k)∗100 (2.1.3)
Table 2.2: Comparison between Conventional 4-PAM transmitter and [1].
4-PAM transmitter Power Dissipation Signal Swing
Conventional 3ItailVdd 1,5Itail
[1] (3Itail +3Itailk )Vdd 3Itail
Results Since the 4-PAM transmitter is used for off-chip connection, the package parasitic effects must be taken into consideration, the simulation diagram is shown in Fig. 2.5. As seen, the package is modeled by two capacitors interconnected by an
2.1 4-PAM Transmitters 21 inductor; there are 4 package models, 2 at the output of the transmitter, and 2 at the far end of a 7.5in micro-strip FR4 transmission line simulating the receiver.
Figure 2.5: Simulation diagram.[1]
Is important to review the termination circuit impedance (Back Impedance) per-formance , a variation of the impedance with frequency is shown in Fig. 2.6, as the frequency goes higher, the impedance of the device goes higher as well, an exponential increasing is observed in the range of 109 Hz.
Figure 2.6: Back impedance frequency response. [1]
The results of the differential output eye diagram are seen in Fig. 2.7, the Eye Diagram at the near end of the line (Fig. 2.7 a), shows a current swing of +/- 4mA with intermediate levels at 1.213mA and -1.209mA and transmit jitter of 6ps. As it was expected, the data eyes were more closed at the receiver, at 8Gbps the signal received present a swing of 312mV and data dependent jitter of 90ps as seen in Fig. 2.7 b. The data eye opening of top, middle and bottom were 94.58mV, 86mV and 89.72mV respectively. At a higher data rate (10Gbps) the data eyes closed a bit more, a swing of only 300mV and data dependent jitter of 94ps were presented (Fig. 2.7 c). The data
eye opening of top, middle and bottom were 82mV, 79mV and 82.42mV respectively. The Table 2.3 shows the performance summary of the transmitter described.
Figure 2.7: Eye diagram at, a) the transmitter at 8Gbps, b) the receiver at 8Gbps, c) the receiver at 10Gbps. [1]
Table 2.3: Performance Summary of [1].
Specification
Technology 180nm,1,8V
Data Rate 10Gbps
Power 10.2mW
Power/Gb 1pJ/b
Medium 7.5in FR4
Reception Swing 300mV
Iout +/- 4mA
BER 10−12
Observations
Current sources Mismatch: Most of the 4-PAM transmitters uses at least 2 current sources ([1], [3], [17], [18], [19], [20]), one with the double of amperage than the other, this is often implemented with current mirrors and the matching between them is important in order to replicate accurately the current magnitu-de, and therefore the amplitude levels. To illustrate this effect, a 500 iterations
2.1 4-PAM Transmitters 23 of Montecarlo simulation was done; the current source 2I of the conventional 4-PAM transmitter was modeled by a NMOS transistor of appropriate dimen-sions, using a typical Gaussian distribution equation (2.1.4) the distribution variations are around of ± 10 % as shown in Fig. 2.8.
σ(∆W/W)( %) = √0,373
W ∗L (2.1.4)
Figure 2.8: Normalized Montecarlo Width Variations.
Figure 2.9: Transmitter Output Current Eye Diagram, a) Nominal, b) Current Sources Mismatch Montecarlo Iterations.
differential output will present level degradations in all 4 PAM levels. In Fig. 2.9 a), the transmitter with no variations is shown, as it can be seen is doesn’t present level degradations, however in Fig. 2.9 b) all the PAM levels present degradations of approximately a 10 % in the vertical opening. It is worth men-tioning that these mismatch variations can be reduced using adequate layout techniques (Multi finger transistors, common centroid topologies among others [21]).
Varying impedance value of the NMOS termination device: Conside-ring that gds and gmb of a MOSFET transistor, depends on the current flowing
through the device and if the current doesn’t change, the impedance neither, however in this caseVds =Vdd−Vout, the output node variations of any 4-PAM
transmitter are inevitable when data is being transmitted, that implies that the termination device current will change and this will affect to the impedance of the device. Its important to take into account these impedance variations becau-se the matching between thebecau-se impedance and the transmission line characteris-tic impedance will impact on the reflected signal coming from the transmission line. [1] does not report those variations, neither the quiescent current of the termination devices which are important for the global power consumption.
2.2.
Pre-Emphasis Circuits
The use of this kind of circuits could impact greatly in the receiver data eye opening, a brief review of Pre-Emphasis circuits are presented in this section.
2.2.1.
Ideal current mode Pre-Emphasis model
An ideal model of a Pre-Emphasis circuit can be modeled by 2 current sources, one from Vdd to the out node and the other from the out node to ground, as shown
in Fig. 2.10 in a dashed box, the use of current sources will give the circuit the ability to add or subtract current depending on the case to compensate the losses of the transmission line. This is valid to 2-PAM transmitters, 4-PAM transmitters or higher.
However, as exposed in [20], many publications won’t consider that depending on the different 4-PAM level transitions the 4-PAM transmitter will require different
2.2 Pre-Emphasis Circuits 25
Figure 2.10: Ideal Pre-Emphasis Model.
Pre-Emphasis currents. To design a Pre-Emphasis circuit it is necessary to propose a new model that takes into account the PAM transition made, this model is seen in Fig. 2.11. This new general model uses 6 current sources of different values that are controlled by 6 switches (S0 toS5), in this model using a bubble code only one switch
can be closed at a time, however it is possible that any switch would be closed at any time.
Figure 2.11: Ideal Pre-Emphasis Model modified to 4-PAM.
Every switch is controlled by the data transition, which can be separate it into 3 categories, small increase/decrease (only 1 PAM level change), medium increa-se/decrease (2 PAM level change) and large increaincrea-se/decrease (3 PAM level change) as shown in Fig. 2.12.
Figure 2.12: Possible Data transitions.
Depending on the closed switch a certain amount of current will be ad-ded/subtracted to the signal trying to compensate the losses of the transmission line. It is important to remark that, the amount of current added/subtracted to each level and the time of duration of that current pulse must be determined by a previous transmission line characterization.
2.2.2.
State of the Art.
In contrast with 4-PAM transmitters, there are no exclusive Pre-Emphasis cir-cuits publications to the author’s knowledge, instead 4-PAM transmitters with Pre-Emphasis circuits are reported [20, 3, 2]. These Pre-Pre-Emphasis circuits perform the addition/subtraction (in other words, correction) using CMOS transistors as current sources controlled by digital circuitry. The Pre-Emphasis circuit used in [2] is shown in Fig. 2.13, basically there are 6 transistors controlled by the nodes SC, SD, MC, MD, BC, BD which corresponds to the 3 cases of charging/discharging, aided with digital circuitry the transistors make the proper correction. The additional transistors connected to the output are related to the functioning of the 4-PAM transmitter in the design.
However, Pre-Emphasis circuits can have the same structure as the 4-PAM trans-mitter as is the case in [3] and shown in Fig. 2.14, the control is done with digital circuitry as well, but in this case the correction is made almost identically as the 4-PAM transmitter is performing the amplitude levels.
Observations Dimensioning and Biasing of Pre-Emphasis transistors: To provide a large current, the voltage Vgs of the MOS transistors has to be large, but connecting
2.2 Pre-Emphasis Circuits 27
Figure 2.13: Pre-Emphasis Circuit.[2]
Figure 2.14: Pre-Emphasis Circuit.[3]
diminish Vgs, and hence a larger transistor size will be required. This issue can be
solved only connecting the essential transistors to the circuit in order to perform the correction.
2.3.
Comparative between works
The Table 2.4 shows a comparison between 4-PAM transmitters, with [3, 20, 2] including a Pre-Emphasis (PE) stage. Those works were published between the years 2002 and 2015, and were implemented in CMOS technology, as in this work.
Before starting the discussion is important to establish that one of the most im-portant is Power per bit (2.3.1) given in J oules/bit this equation is like a Figure of Merit (FOM) between transmitters and its refer to the energy to transmit a data bit. This relationship shows a balance between power consumption and data rate, the transmitter efficiency is greater if the value is lower.
P owerP erBit= P owerConsumption
DataRate (2.3.1)
The 4-PAM transmitters with the larger reception swing, works in voltage mode [22, 20, 2], however only [2] uses a medium of 12in of FR4, that presents greater losses in comparison with 0.7m or 0.8m cable. The transmitters that draw the most published current are [17, 18, 19] with power consumption over 60mW. The trans-mitter working at the higher data rate is [3], however the medium is simulated and the power consumption makes the Power per bit value stand at 1.1pJ/b.
The 4-PAM transmitter of [1] showed the best results. The qualities of using the same CMOS technology and the same type of medium make it directly comparable. Also, it presented the lowest Power per bit reported (1 pJ/b) working with 10.2mW at 10Gbps at a reasonable amount of output current (4mA), besides is the only work that takes into account a parasitic model of the package. That is why the work [1] is going to be our test bench against we are going to be directly compared.
This work aim is to obtain a 4-PAM transmitter insensitive to mismatch between biasing current sources, a transition compensated active termination device, and a Pre-Emphasis circuit that enhance the vertical opening at least 15 %, and finally to keep the Power per Bit below 1.5pJ/b.
2.3 Comparative between works 29 T able 2.4: S tate of the Art. Author PE T ec hnology
Data Rate (Gbps)
P ow er (mW) P ow er p er bit (pJ/b) Medium Rx Swing (mV)
Iout (mA)
BER Observ ations [1] No 180 n, 1 , 8 V 10 10.2 1 7.5in FR4 300 +/-4 10 − 12 P ac kage mo deling, activ ely terminated [3] Y es 65 n, 1 , 2 V 40 45.2 1.1 Ideal resis-tor – – – – [22] No 130 n, 1 , 2 V 10 13.5 1.4 2cm PCB +0.7m ca-ble 1200 – 10 − 12 V oltage mo de [17] No 180 n, 1 , 7 V 7 66 9.4 3cm PCB +0.8m ca-ble 600 39 – – [18] No 180 n, 1 , 8 V 8 98 12.3 – – 52 – – [19] No 180 n, 1 , 8 V 3.2 60 18.8 – 390 33 – – [20] Y es 130 n, 1 , 8 V 10 245 24.5
2cm PCB+ 0.3m
cable 1800 – 10 − 12 V oltage mo de [2] Y es 180 n, 1 , 8 V 1 133 133 12in FR4 1800 – – V oltage mo de
Chapter 3
4-PAM Transmitter Design
In this chapter, 3 new proposals of 4-PAM transmitter are described and their performance was compared, the specifications for the proposals were a data rate of 8Gbps and an output current of 4mA. The objective is to choose the proposal which consumes less power with the wider eye opening characteristics.
3.1.
Proposal 1
Since one of the main issues of the 4-PAM transmitters is the matching of the current sources biasing the circuit; this proposal attempts to address this problem eliminating the need of multiple biasing current sources and replace them with only one current source with a new value ofI, its description and analysis will be explained as follow.
3.1.1.
Description and Analysis
The 3 stages 4-PAM transmitter proposed is shown in a dashed box in Fig. 3.1, it is formed by; the termination device, the biasing current source and the core of the transmitter.
Termination Device: in this case, the termination device is a common node 50Ω passive resistor RT+/−, the value was chosen in order to match it with the
transmission line characteristic impedance.
Biasing Current Source: as said before, this circuit eliminates the need of mul-tiple current sources by using only one current source I, this is proportional to the addition of Itail and 2Itail of the conventional 4-PAM transmitter. The
Figure 3.1: 4-PAM Transmitter proposal 1.
implementation is made with a properly dimensioned NMOS transistor biased with a voltage source V.
Core: in order to have a unique current source, it was necessary to change the conventional 4-PAM transmitters core by adding 2 transistors and chan-ge the input data code from binary code digital (BCD) to thermometer code by using digital circuitry. The core can be divided in two parts: the positive (M0+M1+M2−) and negative (M0−M1−M2−) branches.
The operating principle is simple, but before its explained is necessary to point out some considerations. First, only 3 digital signals from D0+/−, D1+/− andD2+/− must
be at a high level at any time, and therefore the rest (the complement signals) will be in an off state. Second, the NMOS transistorsM0+/− troughM2+/− are all equals,
and they will be carrying the same current (when ON). And finally, the current of
MI is always constant, its Vds is set to be constant (these considerations also apply
to the proposals explained later in this chapter).
As explained before, at any time there are 3 NMOS transistors turned on, they can be from any branch, either positive , negative or even a combination of both, and each transistor will provide 1/3I when ON. So when the positive branch is taking certain current, the negative branch is taking the rest, in order to always carrying a total of I. Therefore I must be divided into three equal parts in order to fulfill Eq. (3.1.1). With this, the circuit is able to provide complementary outputs and hence, the output can be read using a differential amplifier to eliminate the common mode
3.1 Proposal 1 33 or crosstalk [9].
I =IM0++IM1++IM2++IM0−+IM1−+IM2− (3.1.1)
To exemplify the functioning, lets consider an input thermometer code of 011 and its inverse 100 (being the last bit the least significant), the transistors M1+, M0+
and M2− are turned on, and the rest will be off. Therefore, Iout+ = 2/3∗ I and
Iout− = 1/3∗I achieving a total current ofI (Eq. (3.1.1)), so after the current divider
at the output Iout+= 2/6∗I and Iout− = 1/6∗I if RT+/−=RL+/−.
Since the input is thermometer coded, the data bits can only have 4 combinations (000, 001, 011, 111), however the circuit is able to provide proportional current if any data is high. For example, the thermometer data input 001 is equal to a data input of 010 or 100, therefore I+ will be the same in those cases, similarly 011 is equal to
101 and 110, so the core of the 4-PAM transmitter can work even with a different code besides the thermometer code and its inverse, nevertheless this work will only consider thermometer data input. The Table 3.1 resumes the operation of the circuit against different thermometer data input.
Table 3.1: Currents in function of Thermometer input data.
Data (+/-)
D2 D1D0
I+ I− Iout+ Iout−
000/111 0 I 0 I/2
001/110 1/3∗I 2/3∗I 1/6∗I 2/6∗I
011/100 2/3∗I 1/3∗I 2/6∗I 1/6∗I
111/000 I 0 I/2 0
Finally the Table 3.2 summarizes the transistors size (core and current source), biasing voltage value of the current source and the values of the termination and load resistors.
Table 3.2: Device’s values and dimensions of Proposal 1.
Device Value/Dimensions
RT, RL 50Ω
Vbias 0.89V
(W/L)M0∼ 2 14.4µm/0.36µm
3.1.2.
Simulation Results
The results of the transient simulations are shown and discussed in this section. The simulations guidelines were:
Simulation Time:100ns
Data input: Voltage sources controlled by random bits with 0v and Vdd as low
and high level respectively.
Data rate: Equivalent to 8Gbps.
Channel: 12in FR4 transmission line model.
Package model: Not included.
The pack parasitics were not taken into account in order to check the proper functio-ning of the proposal itself.
Figure 3.2: Input Data Voltage Sources.
The data input were voltage sources controlled by random bits with binary levels of 0 volts and Vdd with a data rate equivalent to 8Gbps, as seen in Fig. 3.2, as seen
3.1 Proposal 1 35 the data is in thermometer code, so the sourcesD1+ and D2+ can’t be in an ON state
if D0+ is in an OFF state. The ON voltage is 1.8v and the OFF voltage is 0v for all
cases.
Figure 3.3: Circuit Bias Current.
A current of approximately 8mA was used to bias the core circuit, as shown in Fig. 3.3. When there is a data transition, glitches of no more than 20ps are present in the bias current, the amplitude of those glitches depends on how many PAM levels change, the maximum amplitude of 17mA (3 level change) and a minimum of 6mA (1 level change). These glitches does not affect the operation of the circuit.
Figure 3.4: Biasing Current Source Vds.
in approximately 100ps to a value of 0.43v. A slight variation of 2mV can be seen during the intermediate levels of the transmitter, such variation have not significant impact on the results.
The core transistor currents on the positive branch are shown in Fig. 3.5, every transistor (when ON) carries almost the same amount of current which is 2.68mA, it can be seen that the voltage data input was transformed into current using the NMOS transistors.
Figure 3.5: Current from Core transistorsM0−2.
When there is a transition of any of the signals, an overshooting or undershooting appears, this can be better seen in Fig. 3.6, it presents a maximum amplitude of 1mA and 0.7mA for undershooting and overshooting respectively an a minimum of 0.4mA for both cases. The current source Vds variations are also reflected here causing that
the lower intermediate level instead of being at 2.68mA went a little higher to 2.7mA, this represents a variation of 0.7 %, which is negligible.
3.1 Proposal 1 37
Figure 3.6: Current from Core transistors Overlapped.
Figure 3.7: Positive Branch’s Total current.
The total current provided in the positive branch is shown in Fig. 3.7. The lo-wer level is at 0mA, the intermediate levels are at 2.7mA and 5.37mA, and finally the upper level is at 8.06mA. The levels are at its ideal values except for the high intermediate level, which presents a variation of 0.7 %.
The simulations confirmed that a current divider is seen in the output node (Fig. 3.8, 3.9), the termination resistor and output level spacings are the same, however there is an offset of 0.52mA between those currents. The output current levels are in -0.23mA, 1.09mA, 2.42mA and 3.8mA and for the termination resistor levels are 0.23mA, 1.6mA, 2.95mA and 4.25mA.
Figure 3.8: Current Divider from positive branch.
Figure 3.9: Current Divider from negative branch.
Figure 3.10: Transmitter Output Current.
at -0.23mA, 1.09mA, 2.42mA and 3.8mA for lower, intermediate and upper levels, respectively. It is worth noticing that the transition times are very short, making
3.2 Proposal 2 39 sharp transitions and settling to a value in approximately 50ps, this is due to the use of ideal resistors that does not present any parasitic capacitances.
3.2.
Proposal 2
In proposal 2, a NMOS transistor is used as termination devices, by doing this the power dissipated by the termination resistor is lowered. Also, an auxiliary biasing circuit is introduced in order to bias the NMOS termination transistors.
3.2.1.
Description and Analysis
The modification made to the proposal 1 transmitter (Fig. 3.11) is the replacement of the passive termination resistor with an NMOS transistor in order to provide an impedance of 50Ω and match it to the characteristic impedance of the line; an auxiliary biasing circuit is introduced and to reduce the power consumption the main power supply circuit is halved. It is worth mentioning that the functioning of the transmitter core is the same.
Figure 3.11: 4-PAM transmitter proposal 2.
First, the currentI+/− will depend only in the current to send to the channel and
I+ =Iout++IM T+ (3.2.1)
I− =Iout−+IM T− (3.2.2)
Since the output current in proposal 1 was halved because the termination and the load resistors were of the same value, in this proposal I would take a different value in order to take into account the termination transistor currents as seen in Eq. (3.2.3).
I =Iout++Iout−+IM T1++IM T1− (3.2.3)
Second, in order to properly size and bias the termination transistor (MT) to a
specific resistance value, the Eq. (3.2.4) [5] was used assuming that Vds of MT is 2(Vgs−Vth).
Rds =
1
KpW/L(Vgs−Vth)
(3.2.4)
Where Kp is a constant related to the carrier mobility and the capacitance of
the gate oxide, assuming a fixed W/L (given by design) and Vgs, Rds will be kept
constant, the proposed auxiliary circuit shown in Fig. 3.12 was used to keep Vgs of
MT (Fig. 3.11) at a controlled value.
This circuits is very similar as the core of the 4-PAM transistor, however since the output are voltages in nodes X and Y, a passive resistor is enough to set those voltages. This nodes are controlled by the value of the resistors and the current flowing through the branches due to the input thermometer code of the main circuit (3.11).
Doing a quick analysis, it is easy to determine the voltages VX and VY (Eqs.
(3.2.5),(3.2.6)). It is worth remembering that in the main circuit (Fig. 3.11 the voltage of the output nodes will remain in a valueVdd/2−Iout∗Rout, whereRout is the output
resistance of the circuit.
VX =Vdd−IRBX ∗RBX (3.2.5)
3.2 Proposal 2 41
Figure 3.12: Auxiliary Biasing Circuit.
Where IRBX/Y ∗RBX/Y were chosen to be equal to Iout∗Rout, by doing this the
X/Y nodes and Vout nodes will have the same behavior with different offset values
in order to have a constant Vgs in the termination transistors (MT) as seen in Eq.
(3.2.7).
Vgs =VX −Vout
Vgs =Vdd−IRBX ∗RBX −(Vdd/2−Iout∗Rout)
Vgs =Vdd−Iout∗Rout−Vdd/2 +Iout∗Rout
Vgs =Vdd/2
(3.2.7)
And finally, the Table 3.5 summarizes the value of the load resistors, the voltage source of the current sources and the size of the transistors of the core and current sources (main and auxiliary circuit).
3.2.2.
Simulations Results
The results of the simulation of proposal 2 are presented in this section, it’s im-portant to remark that the simulation guidelines for proposal 2 were the same as proposal 1;
Table 3.3: Device’s values and dimensions of Proposal 2.
Device Value/Dimensions
RL 50Ω
RB 175Ω
VBIAS 0.8V
VBIAS2 0.90V
(W/L)M0∼2 23.04µm/0.36µm
(W/L)I 76.8µm/0.18µm
(W/L)IB 50.4µm/0.36µm
(W/L)M T 72µm/0.18µm
Simulation Time:100ns
Data input: Voltage sources controlled by random bits with 0v and Vdd as low
and high level respectively.
Data rate: Equivalent to 8Gbps.
Channel: 12in FR4 transmission line model.
Package model: Not included.
Also the input dataD0+/−toD2+/−in proposal 2 was the same as proposal 1, by doing
this we guarantee the same simulation conditions in order to make a fair comparison between proposals.
3.2 Proposal 2 43 The current source delivered a current of approximately 8mA as shown in Fig. 3.13, every data transition produces glitches with a duration of no more than 20ps, the amplitude depends on which transition of the PAM levels was made, the bigger the level change the larger the amplitude of the glitch, the minimum peak to peak amplitude of such glitches was 5.6 mA (1 level change) and the maximum was 16.2mA (3 level change). These glitches do not affect the operation of the circuit.
Figure 3.14: Biasing Current SourceVds.
The current sourceVds is seen in Fig. 3.14, glitches of a duration of approximately
80ps are seen to settle in a voltage of 0.43V, it’s important to notice that in certain transitions, the voltage increases a 10 % to settle on a value of 0.47V.
The core transistors currents on the positive branch are shown in Fig. 3.15, every transistor (when ON) carries almost the same amount of current which is 2.66mA, however the current sourceVds introduces a significant error when only a single
tran-sistor of the branch is on, causing that a level increases its value a 10 % settling in 2.92mA. This effect is best seen in Fig. 3.16, a variation is seen in comparison with other amplitude levels, this may cause a systematic level degradation. Additionally, a ringing is appreciated in IM2, this ringing may be associated with the fact that
when M2 is ON, all other transistors are ON (because of the thermometer code).
Also overshooting and undershooting are present in the transition, with a maximum amplitude of 4mA and a minimum of 650µA its effects are negligible. It’s important to remark that since the branches are symmetrical, the same effects are seen in the negative branch.
Figure 3.15: Current from Core transistors.
Figure 3.16: Current from Core transistors overlapped.
The total current of the transistors are shown in Fig. 3.17, some of the effects discussed before also have an influence here, such as the ringing in the upper level, which is highly associated with the transition of the lower to the upper level. The
