Digital counter cell design using carbon nanotube FETs Technology Journal of Applied Researchand

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Availableonlineatwww.sciencedirect.com

Journal of Applied Research and Technology

www.jart.ccadet.unam.mx JournalofAppliedResearchandTechnology15(2017)211–222

Original

Digital counter cell design using carbon nanotube FETs

Mehdi Bagherizadeh

^a,^∗

, Mohammad Hossein Moaiyeri

^b

, Mohammad Eshghi

^b

aDepartmentofComputerEngineering,RafsanjanBranch,IslamicAzadUniversity,Rafsanjan,Iran

bFacultyofElectricalEngineering,ShahidBeheshtiUniversity,G.C.,Tehran,Iran Received24July2015;accepted9December2016

Availableonline22April2017

Abstract

Compressorandcountercellsarethebasicblocksusedtoaccumulatethepartialproductsinamultiplicationprocess.Inthispaper,novelhigh speedandlowpowercarbonnanotubecountercellsaresuggested.Theefficiencyofcircuitsisimprovedbyusingcarbonnanotubefield-effect transistors(CNFETs).Theproposeddesignsare4-to-3,5-to-3,6-to-3,and7-to-3counters.UsingHSPICE,theseproposeddesignsaresimulatedat differentconditions.SimulationresultsconfirmthattheproposeddesignsarethefastestcounterswithlowestPDPindifferentworkingcircumstance.

Keywords:Compressor;Countercell;Carbonnanotubetransistor;Multiplier

1. Introduction

Among the most basic blocks in computer arithmetic are multipliers,whicharecommonlyusedindifferentdigitalsig- nalprocessors.Indifferentapplicationsofcomputingsystems there is growing demands for high-speed multipliers, such as computer graphics, image processing, scientific calcula- tion, and so on (Azarderakhsh & Reyhani-Masoleh, 2013;

Bagherizadeh,Gerami,&Eshghi,2014; Rodríguez-Reséndiz, Gutiérrez-Villalobos,Duarte-Correa,Mendiola-Santiba˜nez, &

Santillán-Méndez, 2012). The speed of a multiplier specifies howfastaprocessorwillrun.Designersarenowmorefocused onlowpowerconsumptionandhighspeedprocessors.Amul- tiplicationoperation conventionallyinvolvesthreeoperational stages:generationofpartialproducts,reductionofpartialprod- ucts to two additive operands,and finally, carry propagation addition.Thepartial productreduction stageis respectfulfor amain part of the totalmultiplication delay,power andarea (Waters&Swartzlander,2010).Hence,inordertoacquirepar- tialproducts,compressorandcountercellsusuallyimplement thisstagebecausetheycontributetothereduction ofthe par-

∗Correspondingauthor.

E-mailaddress:[email protected](M.Bagherizadeh).

PeerReviewundertheresponsibilityofUniversidadNacionalAutónomade México.

tialproductsandthecriticalpath(Jaberipur&Kaivani,2009).

Countersaremuchfasterthanconventionaladdersbecausethey couldactwithoutcarrysignalalongtheirdigitalstages.Counters arethebasicblocks,whichareusedtoacquirethepartialprod- uctsinthemultiplicationprocess(Deng&Chen,2013).Thus, improvingthepowerperformanceofthesestructurescouldlead toremarkablesavingofthepowerusedbytheentiremultiplier.

Becauseoftheminiaturizationofthetransistors,itispossible to increase the number used in each circuit. Thisnano level reductionwillcausesomeacuteproblemssuchasshortchannel effects,remarkable gatecontrol degradationandhighleakage powerconsumption.Asolutiontotheseproblemsisusingcar- bonnanotubefieldeffecttransistors(CNFETs)(Bagherizadeh

& Eshghi, 2011a, 2011b;Perri &Corsonello, 2012). Oneof the most considerable properties of this type of transistor is theabilityofhavingoptionalthresholdvoltagebychangingthe diametersofthenanotubes.ThispropertymakesCNFETssuit- ablefordesigningcircuitswithmultiplethresholdvoltageranges (Bagherizadeh&Eshghi,2011a,2011b).

Inthispaper,fournovelhighspeedandlowPDPCNFET- based counters are proposed. These counters are capable of adding four, five, six or seven bits per decade, andgenerate 3outputs.CNFETswithdifferentthresholdvoltagesareusedto designourproposedcounters.

Intheremainderofthispaper,inSection2,abriefreviewof theCNFETtechnologyispresented.Inthenextsectionrelated

http://dx.doi.org/10.1016/j.jart.2016.12.005

1665-6423/©2017UniversidadNacionalAutónomadeMéxico,CentrodeCienciasAplicadasyDesarrolloTecnológico.Thisisanopenaccessarticleunderthe CCBY-NC-NDlicense(http://creativecommons.org/licenses/by-nc-nd/4.0/).

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worksarediscussed.TheproposedCNFET-basedcountercells arepresentedinSection4.Experimentalresults,analysesand comparisonsarepresentedinSection5,andfinally,Section6 concludesthepaper.

2. Carbonnanotubeﬁeldeffecttransistors(CNFETs) A carbon nanotube (CNT) is an allotrope of carbon with a tubal nanostructure. Transistors, which have carbon nano- tubesastheir channel,arecalledcarbonnanotubefield-effect transistors(Mehrabani&Eshghi,2015).CNTshaveparticular propertiesthatmakethempromisingtobeusedinthefieldof integratedcircuits.Themostimportantandremarkablefeature ofCNFETsistheirspectacularcapabilityincurrentdrivingor currentcarrying,andexperimentshaveshownthatCNFETsare thebest forthisaim (Bagherizadeh&Eshghi, 2011a,2011b;

Lin,Kim,&Lombardi,2009).Withoutanyextrapowerover- head,CNFETs couldoperatefive timesfasterthanCMOS in thebestcase.AnotherfundamentalfeatureofCNTFETsistheir variedbehaviorinmanipulatingthethresholdvoltage(Vth)by adopting anappropriate diameterfor CNTs(Bagherizadeh &

Eshghi,2011a,2011b).

Multi-wallednanotubes(MWNT)consistofmultiplerolled layers(concentric tubes)ofgraphite.Asingle-wallCNTcon- sistsofatube-shapedwallwhichismadeofgraphitewiththe diameterof1–2nm.Amulti-walledCNThasathinnerwall.The wallsofthetubesare34nmeach.Theouterwalldiameterof themulti-walledCNTis2–25nm(Mehrabi,Mirzaee,Moaiyeri, Navi,&Hashemipour,2013).

ACNTisdescribedbyitschiralvector.Thechiralityvec- tor is defined by an ordered pair (n1, n2) that characterize manyelectricalandphysicalpropertiesofthecarbonnanotube (Bagherizadeh & Eshghi, 2011a, 2011b; Mehrabi, Mirzaee, Zamanzadeh,Navi, &Hashemipour,2013;Mehrabi,Navi, &

Hashemipour,2013;Mehrabi,Mirzaee,Moaiyeri,etal.,2013).

ItiscalculatedusingEq.(1):

C_h=n₁ˆa1+n₂ˆa2 (1)

where [â1, â2] are the lattice unit vectors and n1, n2 are positiveintegerswhichspecifythetube’sstructure.Thesingle- walled carbon nanotubes (SWCNT) could be a metal or a semiconductor,ifn1−n2 =/ 3k(k∈Z),thentheSWCNTisa semiconductor;otherwiseitisametal.

ThediameteroftheCNTiscalculatedusingEq.(2)(Alkaldy, Navi,&Sharifi,2014;Bagherizadeh&Eshghi,2011a,2011b;

Mehrabani&Eshghi,2015).

DCNT =0.0783

n²₁+n²₂+n1n2 (2) ThethresholdvoltageofaCNTchannelisapproximatedas theinversefunctionofdiameterandcouldbecomputedasEq.

(3).AspecialthresholdvoltageofaCNFETcouldbeobtained byasuitablediameter(Alkaldyetal.,2014).

V_th≈ E_g 2e =

√3 3

aV_π

eD_CNT ≈ 0.43

D_CNT (3)

whereparametera(≈0.249nm)isthecarbon-to-carbonatom distance,Vπ(∼=3.033eV)isthecarbonπ–πbondenergyinthe tightbondingmodel,andeistheunitelectroncharge,Egisthe bandgap,andDCNTistheCNTdiameter.

There are three kinds of CNFET: The first kind is the MOSFET-likeCNFET(whichcontainsthep-typeCNFETand n-type CNFET),whichoperatesinaunipolar mode;the sec- ond kind is the Schottky barrier (SB) CNFET, which shows ambipolarcharacteristics,butbecauseoftheSBelement,itis notappropriateforhighperformanceapplications;thethirdkind ofCNFET,suitableforlowpowerapplications,istheband-to- band tunneling CNFET that has obviouslylow current in its activemode(Alkaldyetal.,2014).Fig.1showsthreekindsof

Gate Gate

Gate Source

Source Metal

Metal Metal

Metal

Substrate Substrate

Substrate

Metal Metal

Drain Oxide

Oxide

Oxide Drain

Drain Metal

Metal

Source

a b

c

Fig.1.(a)SB-CNFET,(b)T-CNFET,and(c)MOSFET-likeCNFET.

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CNFETs.ACNFEThasrelativelylowoff-currentwhilethetran- sistorisinactive;inotherwords,whentheCNFETisoff,leakage powerconsumptionislow.CNFETshaveelectricalspecifica- tionsandstructuresimilartoMOSFETs,whichfacilitatesthe exploitationandreuseofpreviousMOSFET-basedarchitectures andmanufacturingprocesses(Bagherizadeh&Eshghi,2011a, 2011b).

3. Compresssorandcountercellsintheliterarure

In this section, someof the compressor andcounter cells whicharepresentedintheliteraturearediscussed.

3.1. Compressorcells

Fordifferentcompressorcells,differentdesignsofhighper- formanceandlowpowerhavebeenpresented.Inthissection, someofthesecompressorsarereviewed.

A3-to-2compressorappliesthreeinputs,X1,X2,andX3and producestwo outputs,SUMandCARRY.Thiscellcould also be consideredas afulladder cellwhen thethird inputis the carryinputfrom theprevious compressorblock, orX3=Cin.

In the literature,thereare different implementationsof afull adderoptimizedforoneormorefiguresofmerits,delay,power dissipation,andpower-delayproduct(PDP) (Bagherizadeh&

Eshghi,2011a,2011b;Mehrabi,Mirzaee,Zamanzadeh,etal., 2013;Mehrabi,Navi,etal.,2013;Mehrabi,Mirzaee,Moaiyeri, etal.,2013).

FA

HA

FA

HA X3 X2

X4 X5 X4 X3 X2 X1

SUM COUT1

COUT2 COUT2 COUT1 SUM

a b

c d

X1

FA

HA FA X2 X1 X4 X3

X6 X5

FA

COUT1 SUM COUT2

FA

FA FA X3 X2 X5 X4

X6

FA

COUT1 SUM COUT2 X7 X1

Fig.2.(a)4-to-3,(b)5-to-3,(c)6-to-3,and(d)7-to-3counter.

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A4-to-2 compressorcompresses five partial products bits intothree.ThiscompressorhasfourinputsX1,X2,X3andX4 and two outputs, SUM and CARRY along witha CARRY-IN (CIN)andaCARRY-OUT(COUT).TheCINinputistheout- putfromthepreviouslowersignificantcompressor.TheCOUT is the output to the compressor inthe next significant stage.

Usingtwo 3-to-2 compressorsin series,a4-to-2 compressor couldbesetupaswellthatinvolvesacriticalpathdelayoffour XORs.DifferentalternativeimplementationsusingXORgates andMUX are described in Pishvaie,Jaberipur, andJahanian (2012),BahrepourandSharifi(2013).

A5-to-2compressorblockhasfiveinputsX1,X2,X3,X4,X5, andtwooutputs,SUMandCARRY,alongwithtwoinputcarry bits(CIN1,CIN2)andtwooutputcarrybits(COUT1,COUT2).The inputcarrybitsaretheoutputsfromthepreviouslesssignificant compressorblock.Theoutputcarriesarepassedontothenext highsignificantcompressorblock.Inaddition,a5-to-2compres- sorcouldbesetupusing3-to-2compressors.Itconsistsofthree 3-to-2compressors(fulladders)inseries(Chang,Gu,&Zhang, 2004;Najafi,Timarchi,&Najafi,2014).Thisarchitecturehasa criticalpathdelayofsixXORgates.

InQi,Kim,andChoi(2012),inordertoreducethepower delayproductofamultiplier,differenttypesoftheMUX-based compressorcells are presented. Thesedesignsare for 4-to-2, 5-to-2, and7-to-2compressors. The MUX-based compressor cellsusemuchless transistorsthanthefulladderbasedcom- pressors.

3.2. Countercells

Oneofthemaincomponentstoconstructhighperformance DSPunitsistheparallelcounter.Asthemultipliersizeincreases, designingoptimizedwidercountersare criticalfor itsperfor- mance (Bagherizadeh et al., 2014; Parandeh-Afshar, Verma, Brisk,&Ienne,2010).Acounteris thehardware that counts thenumberoflogic‘1’ofinputtedbits.Countersaredifferent fromcompressors.Theessentialdifferencebetweenacounter andacompressoristhatthecounterhasnointer-stagecarriesand nointer-stageinterconnects.Ontheotherhand,thecompressor hasanumberofcarriesthatcomefromorgototheneighbor- ing cells inthesame stage. Countercells are greatly used in manydifferentscopessuchastriggeringinmultichannelhigh energyspectrometers,digitalnervousnetworks,parallelmulti- pliersandmultipleinputadders(Bahrami&Sadeghiyan,2000;

Mohd,Abed,&Alouneh,2013).

A4-to-3counterisanetworkwith4 inputsand3 outputs, wheretheoutputsshowthecountthe1’sinputs.Asshownin Fig.2(a),a4-to-3counteriscontainedofafulladderandtwo halfaddersinseries.Anotherstructurefor4-to-3counterhas beendesignedinMehrabi,Mirzaee,Zamanzadeh,etal.(2013) (Fig.3).Theactualefficiencyofthesecountercellsextremely dependsontheunderlyingtechnology whichhoststhe imple- mentationof the primary blocks (i.e., MUX,XOR, andFA).

BasedontheCMOSimplementationoftheseprimaryblocks,a totalof80transistorsarerequiredforthe4-to-3counterdesign ofFig.3.

AND XOR

XOR AND

XOR

XOR MUX

X1 X2 X3 X4

COUT1 SUM COUT2

Fig.3.The4-to-3counterinMehrabi,Mirzaee,Zamanzadeh,etal.(2013), Mehrabi,Navi,etal.(2013);Mehrabi,Mirzaee,Moaiyeri,etal.(2013).

A5-to-3counterwillcompressfivepartialproductsintothree outputs.AsshowninFig.2(b),thiscounterisconstructedusing twofulladdersandonehalfadderinseries.Thecountinglimit ofthiscounteriszerotofive.Theconventional5-to-3counter actuallyhasfiveXORgatestogeneratetheoutput.Becauseof itsimportance,researchershaveproposeddifferentmethodsby rearrangingtheXORgatestoreducethedelayinthiscounter.

A5-to-3counterhasbeen designedinChowdhury,Banerjee, Roy,andSaha(2008a,2008b)(Fig.4).Itisahybridstructureof 2-inputXORs,MUXs,anda2-inputANDgate.Incomparison withitsconventional5-to-3counter,itbenefitsfromashorter criticalpath.Atotalof80transistorsarerequiredtodesignthis cellusingaCMOSimplementationofbasicblocks.

A6-to-3countercompresssixpartialproductsintothreeout- puts. The structure of this counteris composed of three full adders and one half adder (Fig. 2(c)). This kind of counter could be used in ahighspeed multiplier toreduce the num- berofpartialproducts.A6-to-3counterhasbeendesignedin Mehrabi, Mirzaee,Zamanzadeh,etal.(2013),Mehrabi, Navi, etal.(2013);Mehrabi,Mirzaee,Moaiyeri,etal.(2013).Itisa

XOR XOR

XOR

SUM COUT1

COUT2

X1 X2 X3 X4

MUX

MUX XOR

XOR AND

X5

Fig.4.The5-to-3counterinChowdhuryetal.(2008a,2008b).

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hybridstructureof2-inputXORs,MUXs,anda2-inputAND gate.Atotalof112transistorsarerequiredtodesignthecellin Fig.5,usingaCMOSimplementationofbasicblocks.

A 7-to-3 counter includes seven inputs and three outputs calledSUM,COUT1andCOUT2.The architectureofacon- ventional7-to-3counterisshowninFig.2(d).Thiscounteris composedoffourfulladders.InGhasemzadeh,Mohabbatian, Akbari, Hadidi, and Khoei (2014), a novel CMOS structure forthe 7-to-3counteris designed.In thisdesign,theoutputs arebasedon thenumberof bitswithvalue ‘1’intruth table.

Another design for the 7-to-3 counter has been proposed in Mohdetal.(2013)(Fig.6).The actualperformanceof these countercellsheavilydependsontheunderlinedtechnologyas well,thathoststheimplementationofthebasicblocks(i.e.,FA, XORandMUX).BasedontheCMOSimplementationofthese basicblocks,atotalof180transistorsarerequiredforthe7-to-3 counterdesignofFig.6.

Inaddition,inDandapat,Ghosal,Sarkar,andMukhopadhyay (2010)differentcounterlogicsaredesignedupontheconceptof thecounterofafulladder.Itcouldbedefinedasasingle-bitadder circuit,whichhasfour/five/six/seveninputsandthreeoutputs.

InJoshy,Prasath,Ravi,andKarman(2012),differentCNFET

XOR

XOR XOR

MUX XOR

MUX

XOR AND

XOR

MUX XOR

X1 X2 X3 X4 X5 X6

SUM COUT1

COUT2

Fig.5.The6-to-3counterinMehrabi,Mirzaee,Zamanzadeh,etal.(2013), Mehrabi,Navi,etal.(2013);Mehrabi,Mirzaee,Moaiyeri,etal.(2013).

MUX COUT2

MUX

SUM

COUT1 X1

X2

X3 X4

X1 X2

X3 X4 X4

X5 X6 X4 X5

X1 X2 X3 X4

X4 X5

X6 X1 X2 X3 X4

Fig.6.The7-to-3counterinMohdetal.(2013).

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c1

c1 0.5M

0.5M 3.5M

X1 X2 X3 X4

Vdd

GND

2.5M

GND A

A

A B

B B

B 1.5M

B

COUT1 COUT2

Vdd

SUM M= Vdd

4

1

2

3 4

5

6

7

8

9 10

11

12

0.783nm

1.4877nm

1.7226nm

1.4877nm

5.2461nm

1.4877nm

1.0179nm

1.4877nm

1.4877nm 1.4877nm 1.0179nm

1.7226nm

Fig.7.Proposed4-to-3counter.

countercellsusingfulladdercellsaredesigned.However,the designofcountercellsincludingfulladdertreeshasarelatively highdelayandconsumesmorepower.Thesecounterstructures also grow quickly with the input vector size in terms of the needednumberoffulladdercells.

In Mehrabi, Navi, etal.(2013) two differentstructures of lowpower andhighspeed 6-to-3and7-to-3compressorsare proposed.CountercellsinthispaperincludeXOR/MUX-based offulladdercellsandaXOR/MUX-basedstructure.

4. Proposeddesignsforcountercells

Inthissection,fourdesignsof4-to-3,5-to-3,6-to-3and7-to-3 countersareproposed.Thesearecomposedofacapacitornet- workandatransistornetwork.Inthesedesigns,CNFETswith differentthresholdvoltagesareusedtodeterminetherequired switchingthresholds.AccordingtoEq.(3),thediameterofthe nanotubescontrolsthethresholdvoltageoftheCNFET,which isusedindifferentcircuitdesigns.Intheremainderofthissec- tion,adesignproposalfordifferentcountercellsispresented.To designthiscounter,propertransistorswithdifferentthreshold voltages(low,normal,andhigh)andappropriateNOTgatescon- taininganNMOSwithVt=vtandaPMOSwith|Vtp|=Vdd−vt are used.In the simulation bychanging n1 andn2 according

to Eq. (2),appropriate DCNT isreached. Therefore,based on Eq.(3),appropriateVthisreached.

4.1. Proposed4-to-3counter

Theproposed4-to-3counterisdesignedbasedonthesimpli- fiedtruthtableinTable1.Thiscircuitincludesasinglearrayof capacitorsandaCNFET-basedthresholddetectornetwork.As indicatedinTable1,theSUMoutputis‘1’,ifthesumoffour inputsisequalto1or3;otherwise,itisequalto‘0’.COUT1is equalto‘1’,ifsumoffourinputsisequalto2or3.TheCOUT2 is‘1’onlywhenthesumofthefourinputsisequalto4.

Fig. 7 shows the detailsof thisdesign for SUM, COUT1, and COUT2. To design this counter, proper transistors with different threshold voltages (low, normal, and high) and

Table1

Simplifiedtruthtableofa4-to-3compressor.

in COUT2 COUT1 SUM

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

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appropriateNOTgatescontaininganNMOSwithVt=vtand aPMOSwith|Vtp|=Vdd−vtareused.Inthisdesign,aNOT gate containing an NMOS transistor with Vt=3.5M and a PMOSwith|Vtp|=Vdd−3.5Misused,where‘M’isequalto Vdd/4.Whenthesumofthe inputsis“four”,thentheoutput of this NOT is “0”; otherwise, it is “1”. Another NOT gate whichisusedinthisdesigncontainsanNMOStransistorwith Vt=1.5M and a PMOS with |Vtp|=Vdd−1.5M. When the sumof the inputs is“zero” or “one”,then the output of this NOTis “1”;otherwiseit is“0”. Whenthe sumof the inputs is“zero”,theNMOS pulldowntransistorwithlow threshold of Vt=0.5M=0.1125volts is “off”; otherwise,it is “on”. In this state, the PMOS pull up transistor with |Vtp|=0.5M is

“on”;otherwiseitis“off”.BothaPMOSandanNMOSwith

|Vt|=2.5Mareusedinthiscounter.Whenthesumoftheinputs is“three”or“four”,thenthesetransistorsare “off”and“on”, andin the other states theyare “on” and “off”, respectively.

Othertransistorshavenormalthresholds(Vt=Vdd/2).

The sameanalysis canbe done for the othertwo COUT1 outputs.TheCOUT2outputcanbeimplementedonlywithtwo NOTgates.Table2showsthestateofalltransistorsfordifferent

Table2

Stateofalltransistorsfordifferentvaluesofin.

in ONtransistors SUM

0 1,3,5,7 0

1 2,3,5,7 1

2 2,4,5,7 0

3 2,4,6,7 1

4 2,4,6,8 0

valuesofthesumoftheinputs.Usingthistechnique,astandard andsymmetriccircuitisobtained.

A5-to-3compressorhas5inputs,X1,X2,X3,X4,X5andthree outputs,SUM, COUT1, andCOUT2. Asimplifiedtruth table ofthiscircuitisshowninTable3.Thistruthtableissimilarto Table1,buttheonerowforthesumofinputsequals5.Therefore, the circuit for COUT1and COUT2remains unchanged, with respecttothe4-to-3compressor,andonlythecircuitfortheSUM

c1

c1 0.5M

0.5M 3.5M

X1 X2 X3 X4

Vdd

GND

2.5M

GND A

A

A B

B B

B 1.5M

B

COUT1 COUT2

Vdd

SUM M= Vdd

5

1

2

3

4

5

6

7

8

9 10

11

12

13

14

4.5M

X5 c1

0.7047nm

1.4877nm 1.4877nm

1.4877nm 1.4877nm 1.4877nm

1.4877nm

6.5772nm

6.5772nm 1.4877nm

1.4877nm 6.5772nm

0.9396nm

2.1924nm

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c1

c1 0.5M

0.5M 3.5M

X1 X2 X3 X4

Vdd

GND

2.5M

GND A

A

A B

B B

B 1.5M

B

COUT1 COUT2

Vdd

SUM M= Vdd

6

1

2

3 4

5

6

7

8

9 10

11

12

13

14 5.5M

C

5.5M

5.5M X5

X6 c1

c1

0.7047nm

1.4877nm ^1.4877nm

1.4877nm

1.4877nm 1.4877nm 1.4877nm

1.0962^nm 2.5839nm

7.9083nm 1.566nm

0.8613nm

1.4877nm

1.4877^nm 0.8613nm

7.9083nm

2.5839nm

0.7047nm

needsaslightmodification.However,thethresholdvoltageof allthetransistorsarechangedbecauseM=Vdd/5.Fig.8shows acompletecircuitforthe5-to-3counterproposed.

A6-to-3counterhas6inputs,X1,X2, X3,X4,X5,X6and threeoutputs,SUM,COUT1,andCOUT2.Thesimplifiedtruth tableof thiscircuit issimilartoTable3,butthe onerowfor thesumofinputsequals6.Asaresult,thecircuitforCOUT2 remainsunchanged,withrespecttothe5-to-3compressorand

Table3

Simplifiedtruthtableofa5-to-3counter.

in COUT2 COUT1 SUM

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

thecircuitfortheCOUT1andSUMneedsslightmodifications.

Thethresholdvoltagesofallthetransistorsarechangedbecause M=Vdd/6. Fig. 9 shows the complete circuit for the 6-to-3 counterproposed.

A7-to-3counterhas7inputs,X1,X2,X3,X4,X5,X6,X7and threeoutputs,SUM,COUT1,andCOUT2.Thesimplifiedtruth tableofthiscircuitissimilartothesimplifiedtruthtableofthe 6-to-3counter,buttheonerowforthesumofinputsequals7.

Hence,thecircuitforCOUT1andCOUT2remainsunchanged withrespecttothe 6-to-3counter,andonlythe circuitforthe SUMneeds aslight change.The thresholdvoltagesof allthe transistors arechangedbecauseM=Vdd/7.Fig.10showsthe completecircuitforthe7-to-3counterproposed.

5. Simulationresults

AllthedesignsproposedforthecountersbasedonCNFET described inSection4 are simulatedusing HSPICE. Inthese

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c1

c1 0.5M

0.5M 3.5M

X1 X2 X3 X4

Vdd

GND

2.5M

GND A

A

A B

B B

B 1.5M

B

COUT1 COUT2

Vdd

SUM M= Vdd

7

1

2

3 4

5

6

7

8

9 10

11

12

13

14 5.5M

C

5.5M

6.5M

X5 X6 X7

c1 c1 c1

0.7047nm

1.4877nm 1.4877nm

1.4877nm

1.4877nm 1.4877^nm

1.4877nm 1.4877nm

1.4877nm

1.0179nm 1.7226

9.2394nm

9.2394nm 1.8009nm

1.0179nm

0.7047nm

0.8613nm

3.0537nm

0.8613nm

simulations,thecompactmodel,presentedinDengandWong (2007a, 2007b) is employed for the CNFET circuits. This standardmodelhasbeendesignedforunipolarandMOSFET- likeCNFETdevices.Eachtransistorinthismodelmayconsistof oneormoreCNTs.The32nmPTMCMOStechnologyhasbeen used for simulating CMOS circuits. Thesesimulation results

containthreecommonfiguresofmerits:delay,powerdissipation,andpower-delayproduct(PDP).Inallofthesesimulations, theroomtemperatureisconsidered. Averagepowerconsump- tion during alongperiod of timeis consideredas the power consumptionparameter.Thedelayiscalculatedfrom50%volt- agelevel oftheinputto50%voltageleveloftheoutput.PDP

Table4

Simulationresultsforcounters@250MHzwith2.1fFloadin0.65V.

Design Delay(ps) Power(␮W) PDP(fJ)

4-to-3counterinMehrabi,Mirzaee,Zamanzadeh,etal.

(2013),Mehrabi,Navi,etal.(2013);Mehrabi, Mirzaee,Moaiyeri,etal.(2013)

1341 0.077831 0.10437

Proposed4-to-3counter 53.194 0.31318 0.016659

5-to-3counterinChowdhuryetal.(2008a,2008b) 1564.1 0.069825 0.10921

1849.1 0.10424 0.19276

7-to-3counterinMohdetal.(2013) 1892.5 0.22321 0.42241

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Table5

Design Delay(ps) Power(␮W) PDP(fJ)

473.22 0.13005 0.061543

593.63 0.15557 0.092352

Table6

Design Delay(pS) Power(␮W) PDP×E−15(fJ)

965.14 0.1361 0.13142

1423.6 0.2346 0.33410

isthemultiplicationoftheaveragepowerconsumptionandthe maximumdelay.Tomeasurethecelldelay,allthepossibletran- sitionshavebeengeneratedviatestpatternsanditisappliedfor allthestructures.

Thearchitectures proposedare comparedtothebest exist- ing counter architectures interms of power, delay, andPDP.

Forthoroughevaluationoffunctionalityofthedesignsinvar- iousconditions,simulationswereperformedatvarioussupply voltagesandroomtemperature,loadsandfrequencies.Allthe designshavebeensimulatedatroomtemperatureat0.65,and 0.5supply voltages, operating frequencies equal to100MHz and250MHz,anddifferentloadcapacitances.

Forcomparisons,thebestpreviousworksondifferentcounter cellswereselected(Chowdhuryetal.,2008a,2008b;Mohdetal., 2013).First,thecircuitsaresimulatedat0.65Vand0.5Vsupply voltagesandat250MHzoperating frequencywith2.1fFout- putloadcapacitance.Theresultsofthissimulationarerevealed inTables 4 and5, respectively. According tothe experimen- tal results, designsproposed have the lowestdelay andPDP comparedtotheotherdesignsatallsupplyvoltages.

Inthesecondexperimentation,allthecircuitsweresimulated atthe discussed 0.65supply voltageand100MHzfrequency using2.1fFoutputcapacitor.ItiscomprehendedfromTable6.

ThedesignsproposedhavethebestPDPandpowerincompar- isonwiththeothercircuits.

0.00E+00 5.00E-17 1.00E-16 1.50E-16 2.00E-16 2.50E-16

70 60 50 40 30 20 10 0

PDP

Temperature

Proposed 7-to-3 counter Proposed 6-to-3 counter Proposed 5-to-3 counter Proposed 4-to-3 counter

Fig.11.PDPversusdifferenttemperatures.

Another important feature of the circuitswhichshould be consideredistheirimmunitytoambienttemperaturevariations.

Thus,forinvestigatingtheirsensitivitytotemperaturevariation andnoises,thecircuitsproposedweresimulatedinavastrange of temperatures,from0^◦Cupto70^◦Cat0.65Vsupplyvolt- ageand250MHzoperatingfrequencywith2.1fFoutputload capacitance.TheresultsareplottedinFig.11.Thisfigureshows that the proposed design operates correctly with low energy consumptionvariationatdifferentambienttemperatures.

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6 5

4 3

2 1

4-to-3 counter 1.15E-17 1.62E-17 2.11E-17 2.66E-17 3.25E-17 3.92E-17 5-to-3 counter 3.72E-17 4.59E-17 5.51E-17 6.48E-17 7.48E-17 8.58E-17 6-to-3 counter 9.22E-17 1.17E-16 1.40E-16 1.63E-16 1.85E-16 2.08E-16 7-to-3 counter 6.57E-17 8.17E-17 9.62E-17 1.11E-16 1.25E-16 1.41E-16

0.00E+00 5.00E-17 1.00E-16 1.50E-16 2.00E-16 2.50E-16

PDP

PDP versus load capacitor in the counter cells(Vdd=0.65, @250MHZ)

Fig.12.PDPversusdifferentcapacitors.

Table7

Thenumberofelementsindifferentcountercells.

Design Numberofdevices

4-to-3counterinMehrabi,Mirzaee,Zamanzadeh,etal.(2013),Mehrabi,Navi,etal.(2013);Mehrabi,Mirzaee,Moaiyeri,etal.(2013) 60

Proposed4-to-3counter 26

5-to-3counterinChowdhuryetal.(2008a,2008b) 72

6-to-3counterinMehrabi,Mirzaee,Zamanzadeh,etal.(2013),Mehrabi,Navi,etal.(2013);Mehrabi,Mirzaee,Moaiyeri,etal.(2013) 100

7-to-3counterinMohdetal.(2013) 192

Drivingcapability isavery importantmetric for thelogic gates.Thus,inthisworkthedrivingcapabilityoftheproposed structuresisalsoscrutinized.Thedesignsproposedaresimu- latedusingavarietyofoutputloadcapacitors,rangingfrom1 upto6fF,at0.65Vsupplyvoltageand250MHzfrequency.The PDPofthedifferentcounterdesigns,againsttheloadcapacitor variation,areschemedinFig.12.

Table7indicatesthe numberof elementsused indifferent structures.Asshowninthistable,thedesignsproposedhavea lowertransistorincomparisontootherdesigns.

6. Conclusion

Thecarbonnanotubefield-effecttransistor(CNFET)isone ofthenewdevicestodesignlowpowerandhighperformance circuits. In a multiplication process, to accumulate partial products,compressorandcountercellsareused.3-to-2,4-to-2, and5-to-2compressorsdonothaveenoughcapabilitytodesign high-bitsize multipliers.In thispaper, fournovelhighspeed andlow powercarbonnanotubecountercells wereproposed.

These counters were capable to add 4 or 5 or 6 or 7 bits per decade, and generate 3 outputs. CNFETs with different

thresholdvoltageswereusedtodesignourproposedcounters.

The counters proposed were simulated using HSPICE. The simulation results containedthree common figuresof merits:

delay,powerdissipation,andpower-delayproduct(PDP).The simulationresultsindicatethatthedesignsproposedconsume lowpowerandworkproperly.Ourproposedcountersaremore effectiveforhighordermultiplications.

Conﬂictofinterest

Theauthorshavenoconflictsofinteresttodeclare.

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