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COMPUTERS ORGANIZATION

2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING

UNIT 3 - ARITMETHIC-LOGIC UNIT

JOSÉ GARCÍA RODRÍGUEZ

JOSÉ ANTONIO SERRA PÉREZ

(2)

Arithmetic Logic Unit

 Introduction

 Logic Operations

 Addition and subtraction



Carry propagated adder (CPA)



Adder-Subtractor circuit



Overflow

ALU



Overflow



Carry Look-ahead Adder (CLA)

 Multiplication



Binary multiplication without sign



Binary multiplication with sign



Booth Algorithm

(3)

Introduction

B C D E

Z C O

A TEMP

ALU

Introduction

 Arithmetic and logic operator (one or more)

 Accumulator

 One or more temporal registers

 Result flags



Carry (C)



Negative (N)



Overflow (O or V)



Zero (Z)

(4)

Logic operations



Easy to implement ⇒ Direct correspondence with the Hardware.



Logic gates AND, OR, XOR, INVERTER,...

Operation Logic

Operations

Operation

A

B Result

00

01

10

(5)

Addition and subtraction

Inputs Outputs

X Y S C

0 0 0 0

0 1 1 0

Y X C

Y X

Y X Y

X S

=

=

⋅ +

=

Binary half-adder (H.A.)

Half-adder

1 0 1 0

1 1 0 1

A B

S

H.A. C

A

B

C

S

H.A.

(6)

Full Adder (F.A.)

Addition and Subtraction

A B

S Cin

Cout

F.A.

Inputs Outputs

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

Cout 0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Cin B

Cin A

B A Cout

Cin B

A Cin

B A Cin

B A Cin

B A S

⋅ +

⋅ +

=

⋅ +

⋅ +

⋅ +

=

(7)

Full Adder (F.A.)

Addition and Subtraction

• Usign half-adders (H.A.)

H.A.

F.A.

S H.A.

A S

S

Cin

C Cout

B C

(8)

Full Adder (F.A.)

Addition and Subtraction

• Usign gates

(9)

Carry Propagated Adder

Addition and Subtraction



To add two numbers of n bits, n full adder should be placed one after another.



Carry is propagated from one stage to the next one:

Carry Propagated Adder.

FA A

3

B

3

C

2

S

3

C

4

FA

A

2

B

2

C

2

S

2

FA A

1

B

1

C

1

S

1

FA A

0

B

0

C

0

S

0

(10)

Carry Propagated Adder



Adders built with logic gates using the expression:

Cin B

Cin A

B A Cout

Cin B

A Cin

B A Cin

B A Cin

B A S

⋅ +

⋅ +

=

⋅ +

⋅ +

⋅ +

=

Addition and Subtraction

FA A

3

B

3

C

2

C

4

FA

A

2

B

2

C

2

FA A

1

B

1

C

1

FA A

0

B

0

C

0

3T 2T

5T 4T

7T 6T

8T 9T

(11)

Carry Propagated Adder



Full adders built with half-adders

A

3

B

3

B

2

A

2

B

1

A

1

B

0

A

0

Addition and Subtraction

Cin

S Cout A

B

FA A

3

B

3

C

2

S

3

C

4

FA

A

2

B

2

C

2

S

2

FA A

1

B

1

C

1

S

1

FA A

0

B

0

C

0

S

0

2T 3T

4T 5T

6T 7T

9T 8T

( n ) T

Time

Total _ = 2 ⋅ + 1

(12)

Subtractor circuit



The circuit works with numbers in two’s complement notation.



A - B = A + (C1(B) + 1)

Addition and Subtraction

A

3

B

3

B

2

A

2

B

1

A

1

B

0

A

0

FA

C

2

S

3

C

4

FA

C

2

S

2

FA

C

1

S

1

FA

C

0

=1

S

0

(13)

Adder-Subtractor Circuit

Addition and Subtraction

S/A B

i

FA input

0 0 0

0 1 1

1 0 1

1 1 0

( n ) T Time

Total _ = 2 + 1

FA A

3

B

3

C

2

S

3

C

4

FA

A

2

B

2

C

2

S

2

FA A

1

B

1

C

1

S

1

FA A

0

B

0

C

0

S

0

R/S

(14)

Overflow detection

Addition and Subtraction

Two’s complement Adder-Substractor with overflow detection

A

3

B

3

B

2

A

2

B

1

A

1

B

0

A

0

R/S

FA

C

3

S

3

C

4

FA

C

2

S

2

FA

C

1

S

1

FA C

0

S

0

(15)

Overflow Detection

Addition and Subtraction

1. Case Addition of two positive numbers S

C4 C3 C2 C1 0 1 1 1

0 1 1 1 0 1 1 1

1 1 1 0 OV

2. Case Addition of two negative numbers S

C4 C3 C2 C1 1 0 1 1

1 0 0 1 1 0 1 1

0 1 0 0 OV

(16)

Carry Look-ahead Adder

 Assume A and B to be 4 bits numbers

 Carry generating signal:

 Carry propagating signal:

Addition and Subtraction

i i

i a b

G = ⋅

 

=

=

i + i

i i

i

b a

P

b a

P

 Carry on stage i:

 Characterized for A and B:

 

= i + i

i a b

P

1 i i

i

i G P C

C = + ⋅

0 1 1

1

1 0

0 0

C P G

C

C P G

C

⋅ +

=

⋅ +

=

(17)

Carry Look-ahead Adder

 Expanding the expressions depending on C -1 :

Addition and Subtraction

1 0

1 2

0 1

2 1

2 2

2

1 0

1 0

1 1

1

1 0

0 0

C P

P P

G P

P G

P G

C

C P

P G

P G

C

C P

G C

⋅ +

⋅ +

⋅ +

=

⋅ +

⋅ +

=

⋅ +

=

 Carries depend on a i and b i .

 These expressions are resolved as addition of products.

 Three leves of logic gates are needed to get each carry.

1 0

1 2

3 0

1 2

3 1

2 3

2 3

3 3

1 0

1 2

0 1

2 1

2 2

2

C P

P P

P G

P P

P G

P P

G P

G C

C P

P P

G P

P G

P G

C

⋅ +

⋅ +

⋅ +

⋅ +

=

⋅ +

⋅ +

⋅ +

=

(18)

Carry Look-ahead Adder

Addition and

Subtraction a

3

∑ ∑

∑ ∑

b

3

a

2

b

2

a

1

∑ ∑

∑ ∑

b

1

a

0

∑ ∑

b

0

∑ ∑

∑ ∑

g

3

p

3

S

3

c

2

∑ ∑ ∑ ∑

g

2

p

2

S

2

c

1

∑ ∑ ∑ ∑

g

1

p

1

S

1

c

0

∑ ∑ ∑ ∑

g

0

p

0

S

0

c

-1

Look-ahead Carry Generator

c

3

(19)

Carry Look-ahead Adder

Addition and Subtraction

a

3

b

3

g

3

p

3

S

3

c

2

a

2

∑ ∑ ∑

b

2

g

2

p

2

S

2

c

1

a

1

b

1

g

1

p

1

S

1

c

0

a

0

∑ ∑

∑ ∑

b

0

g

0

p

0

S

0

c

-1

1T 1T

4T 3T 3T

3T

4T 4T 4T

1T 1T 1T 1T

1T 1T S

3

S

2

S

1

S

0

Look-ahead Carry Generator

c

3

3T

1T 1T 1T 1T

1T 1T 1T 1T

a

i

b

i

H.A.

C

i-1

F.A.

S

i

c

i

H.A.

1T 3T

4T

Adders built

with half-adders

(20)

Example (8 bits CLA)

Addition and

Subtraction a

7

∑ ∑

∑ ∑

b

7

g p

c

6

a

6

∑ ∑

∑ ∑

b

6

g p

c

5

a

5

∑ ∑ ∑

b

5

g5p

c

4

a

4

∑ ∑ ∑

b

4

g p

c

3

a

3

∑ ∑

b

3

g p

c

2

a

2

b

2

g p

c

1

a

1

b

1

g1p

c

0

a

0

∑ ∑

b

0

g p

c

-1

g7 p7

S

7 g6 p6

S

6

g5p5

S

5

g4p4

S

4

Look-ahead carry generator

c

7

g3 p3

S

3 g2p2

S

2

g1p1

S

1

g0p0

S

0

Look-ahead carry generator

Calculate the delay in this CLA supposing that the adders are

(21)

Example ( 4 bits CLA)

Addition

and

Subtraction

(22)

Example (4 bits CLA)

Addition and Subtraction

C3 C2 C1 C0 C3 C2 C1 C0

0 1 1 1 1 1 1

0 1 1 1 1 0 1 0

0 1 1 1 1 1 1 1

1 1 1 0 1 0 0 1

(23)

Multiplication

Multiplication



Sums and shifts algorithm



If multiplicand has n bits and multiplier has m bits, them the product will have n+m bits.



Binary multiplication: simple as you only multiply by 1 or by 0.

Multiplicand 5 3 2

Multiplier 4 3 1

5 3 2

1 5 9 6

2 1 2 8

Product 2 2 9 2 9 2

(24)

Binary multipication without sign

Multiplication

Repeat n times

If bit 0 of multiplier=1 then

Sum the multiplicand to the left half of the product and place the result int the left half of the product

End if

Shift the product register 1 bit to the right Shift the multiplier register 1 bit to the right End repeat

Preliminary Version

ALU

Multiplicand

Multiplier

Right shift Sum

Right shift

n bits

n bits

(25)

Binary multiplication without sign

Multiplication

Preliminary Version

Multiplicand

1 0 1 1

Multiplier

1 1 0 1

1 0 1 1

0 0 0 0

1 0 1 1

1 0 1 1

Product

1 0 0 0 1 1 1 1

ALU

Multiplicand

Multiplier

Product

Right shift

Write Sum

Right shift

Control n bits

n bits

2n bits C

Product

1 0 0 0 1 1 1 1

(26)

Binary multiplication without sign

Multiplication

Repeat n times

If bit 0 of product register=1 then

Sum the multiplicand to the left half of the product and place the result in the left half of the product.

End if

Shift the product register 1 bit to the right End repeat

Final Version

ALU

Multiplicand

Right shift Sum

n bits

(27)

Binary multiplication without sign

Multiplication

ALU

Multiplicand

Sum

10(d Iteration 0 Initial values 1 0 1 0

ALU

Multiplier Product

Right shift

Write

Control

0 0 0 0 0 0 1 0 1

5(d

(28)

Binary multiplication without sign

Multiplication

ALU

Multiplicand

Sum 1 0 1 0

Iteration 1

Product + Multiplicand

ALU

Multiplier Product

Right shift

Write

Control

0 1 0 1 0 0 1 0 1

(29)

Binary multiplication without sign

Multiplication

ALU

Multiplicand

Sum 1 0 1 0

Iteration 1 Right shift P

ALU

Multiplier Product

Right shift

Write

Control

0 0 1 0 1 0 0 1 0

(30)

Binary multiplication without sign

Multiplication

ALU

Multiplicand

Sum 1 0 1 0

Iteration 2 Right shift P

ALU

Multiplier Product

Right shift

Write

Control

0 0 0 1 0 1 0 0 1

(31)

Binary multiplication without sign

Multiplication

ALU

Multiplicand

Sum 1 0 1 0

Iteration 3

Product + Multiplicand

ALU

Multiplier Product

Right shift

Write

Control

0 1 1 0 0 1 0 0 1

(32)

Binary multiplication without sign

Multiplication

ALU

Multiplicand

Sum 1 0 1 0

Iteration 3 Right shift P

ALU

Multiplier Product

Right shift

Write

Control

0 0 1 1 0 0 1 0 0

(33)

Binary multiplication without sign

Multiplication

ALU

Multiplicand

Sum 1 0 1 0

Iteration 4 Right shift P

ALU

Multiplier Product

Right shift

Write

Control

0 0 0 1 1 0 0 1 0

50(d

(34)

Binary multiplication without sign

Multiplication Multiplicand = 1010

Multiplier = 0101

Product Multiplicand Action Iteration

0000 0101 1010 Initial values 0

1010 0101 1010 Sum prod. and multiplicand 1

1010 0101 1010 Sum prod. and multiplicand 1

0101 0010 1010 Right shift prod. 1 bit 1

0010 1001 1010 Right shift prod. 1 bit 2

1100 1001 1010 Sum prod. and multiplicand 3

0110 0100 1010 Right shift prod. 1 bit 3

(35)

Fast multiplication

Multiplication

(36)

Binary multiplication with sign

Multiplication



Assume two’s complement numbers



A = 1010 y B = 0011



Apply sums and shifts algorithm

1 0 1 0 x 0 0 1 1

1 0 1 0 x 0 0 1 1 x 0 0 1 1

1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0

0 0 1 1 1 1 0

x 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 0 1 1 1 0

(37)

Booth Algorithm



Assume Multiplicand = 2 and Multiplier = 7 (binaries 0010 x 0111)



Booth expressed 7 = 8 - 1 and replaced the multiplier by this decomposition:

0111 = 1000 - 0001 = +100-1

Multiplication

0111 = 1000 - 0001 = +100-1

0 0 1 0 Multiplicand

x +1 0 0 -1 Multiplier according to A. Booth 1 1 1 1 1 1 1 0 Multiplicand subtraction

0 0 0 0 0 0 2 shifts (2 zeros in the multiplier)

0 0 0 1 0 Multiplicand addition

0 0 0 0 1 1 1 0

(38)

Booth Algorithm

Multiplication

Current Bit Bit on the left Replacement

0 0 0 (no transition)

0 1 -1 (transition to negative)

1 0 +1 (transition to positive)

1 1 0 (no transition)

Example: Multiplicand = 11101110 y Multiplier = 01111010 Example: Multiplicand = 11101110 y Multiplier = 01111010 Multiplier according to Booth = +1000-1+1-10

1 1 1 0 1 1 1 0

x +1 0 0 0 -1 +1 -1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

1 1 1 1 1 1 1 1 1 0 1 1 1 0

(39)

Booth Algorithm

Multiplication

q

-1

=0

Repeat n times

If q

0

= 1 and q

-1

= 0 then

Product

h

= product

h

- Multiplicand If q

0

= 0 and q

-1

=1 then

Product

h

= Product

h

+ Multiplicand Arithmetic shift to the right of Product and q

-1

End repeat.

ALU

Multiplicand

Multiplier Product

Right shift Sum/Subt.

Control n bits

2n bits

q

-1

q

0

End repeat.

(40)

Booth Algorithm

Multiplication

Multiplicand Product q-1 Action Itertion

1010 0000 1110

0

Initial values 0

1010 0000 1110 0 00 → No operation 1

Multiplicand = 1010 Multiplier = 1110

1010 0000 0111

0

Right shift 1

1010 0110 0111 0 10 → Subtraction 2

1010 0011 0011

1

Right shift 2

1010 0011 0011 1 11 → No operation 3

1010 0001 1001

1

Right shift 3

1010 0001 1001 1 11 → No operation 4

1010

0000 1100

1 Right shift 4

(41)

Division



Division can be expressed as:

Dividend = Quotient x Divisor + Remainder



The remainder is smaller than the divisor. Double of space should be reserved for the dividend.



Assume positive operands.

Division

Dividend → 10010011 1011 ←Divisor 10010 01101 ←Quotient 1011

001110 1011

001111 1011

0100 ←Remainder

(42)

Algorithm with restoration

Division

Repeat n times

Shift dividend to the left

Dividend

h

= Dividend

h

- Divisor If Dividend

h

< 0 then (does not fit)

q

0

=0

Dividend

h

= Dividend

h

+ Divisor (restore) else

q

0

=1 end if end if end repeat

ALU

Divisor

Dividend

Left shift Sum/Subt.

Control n bits

q

0

(43)

Algorithm with restoration

Division Dividend Divisor Action Iteration

0101 0011 0110 Initial values 0

1010 011_ 0110 Shift 1 bit to the left 1

0100 011_ 0110 Restar 1

0100 0111 0110 Dividend

h

> 0 ⇒ q

0

= 1 1

1000 111_ 0110 Shift 1 bit to the left 2

0010 111_ 0110 Dividend

h

- Divisor (Subtract) 2 0010 1111 0110 Dividend

h

> 0 ⇒ q

0

= 1 2

0101 111_ 0110 Shift 1 bit to the left 3

1111 111_ 0110 Dividend

h

- Divisor (Subtract) 3 1111 1110 0110 Dividend

h

<= 0 ⇒ q

0

= 0 3 0101 1110 0110 Dividend

h

+ Divisor (Restore) 3

1011 110_ 0110 Shift 1 bit to the left 4

0101 110_ 0110 Dividend

h

- Divisor (Subtract) 4 0101 1101 0110 Dividend

h

> 0 ⇒ q

0

= 1 4 ↑ ↑

Rem. Quot.

(44)

Algorithm without restoration

Division

Dividend

h

= Dividend

h

- Divisor Repeat n times

If Dividend

h

< 0 then

Shift the Dividend to the left Dividend

h

= Dividend

h

+ Divisor Else

Shift the Dividend to the left Dividend

h

= Dividend

h

- Divisor End if

If Dividend

h

< 0 then q

0

=0

Else

q

0

=1 End if End repeat

ALU

Divisor

Left shift Sum/Subt.

n bits

(45)

Algorithm without restoration

Division

Dividend Divisor Action Iteration

0000 0111 0010 Initial values 0

1110 0111 0010 Dividend

h

- Divisor 0

1100 111_ 0010 Dividend

h

< 0 ⇒ Shift left 1

1110 111_ 0010 Dividend

h

+ Divisor 1

1110 1110 0010 Dividend

h

< 0 ⇒ q

0

= 0 1

1101 110_ 0010 Dividend

h

< 0 ⇒ Shift left 2

1101 110_ 0010 Dividend

h

< 0 ⇒ Shift left 2

1111 110_ 0010 Dividend

h

+ Divisor 2

1111 1100 0010 Dividend

h

< 0 ⇒ q

0

= 0 2

1111 100_ 0010 Dividend

h

< 0 ⇒ Shift left 3

0001 100_ 0010 Dividend

h

+ Divisor 3

0001 1001 0010 Dividend

h

>= 0 q

0

= 1 3

0011 001_ 0010 Dividend

h

> 0 ⇒ Shift left 4

0001 001_ 0010 Dividend

h

- Divisor 4

0001 0011 0010 Dividend

h

> 0 ⇒ q

0

= 1 4

↑ ↑

Remain. Quotient

(46)

Conclusions

 Adders



Temporal problems with Carry Propagated Adder, specially if n high.



Carry Look-ahead Adders improve response time of the adders.

 Multiplication



Problems with the multiplication of signed numbers.

Conclusions



Booth algorithm allows to multiply two’s complement

numbers and sometimes it reduces the number of operations if there is 1’s or 0’s chains in the multiplier.

 Division



Algorithm with restoration for positive numbers. For negative

numbers, the sign must be preprocessed. The result’s sign will

depend on that.

Referencias

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