A PROXIMACIÓN CONCEPTUAL

High-level languages make writing, debugging and verification of complex applications more efficient. The degree of how high-level a programming language can be depends on the context. For a VLSI engineer, VHDL is considered high-level when he considers custom design, for firmware engineer C is seen as high-level but for a web programmer C is very low-level compared to JavaScript. Each programming language is built for a need. C was developed for

2.3. High-Level Synthesis

(a) Calypto Catapult.

(b) Forte Cynthesizer.

(c) NEC CyberWorkbench.

Figure 2.8 – Three of the most used third generation HLS in the market. The three of them focuses on HLS for ASICs. Catapult and recently CyberWorkbench offers also FPGA support.

executing sequential code on a sequential processor and VHDL and Verilog were designed for replacing hand-written RTL designs.

Most of the programming languages today are sequential. Although, parallel processors are becoming the standard i.e. multi-core and many cores CPUs, general purpose GPUs, and

hybrids multi-core besides an FPGA. Currently there is no parallel languages that target all of them with a single representation. As discussed, for classic programming language like C, libraries are used for exploiting the parallelism, only recently there is native thread support within C++11. Currently only data-parallelism is efficiently supported by OpenCL and CUDA APIs for GPGPUs. FPGAs are natural parallel machines, and Verilog and VHDL exploit their full capability on task and data parallelism, but HDL languages are unacceptable to most application software developers.

In this section, the state of the art of HLS languages and their corresponding tool is given, with the majority of those being C based.

C-like HLS Languages

One of earliest C-to-Gates tools was Cones [55]. It synthesizes single functions, a cone, into combinational blocks. Those blocks were modeled in the C programming language, using assignments, branching, loops and iterative constraints. Ku and De Micheli developed Hard- wareC [56] for the input of the Olympus [38] synthesis system. HardwareC is a behavioral hardware language with C-like syntax and much larger expressing power than Cones. Hard- wareC has extensive support for hardware-like structure and hierarchy, supports concurrency, structural and timing constraints. The Transmogrifier C [57], now called FpgaC, is a small C subset that supports branches, loops, and preprocessor directives. As a disadvantage it does not support multiplication, division, pointers, arrays, structures, or recursion. Celoxica Handle-C extends the C language with constructs for parallel statements and Occam-like communications. CompiLogic C2Verilog or C Level Design, now part of Synopsis, the compiler supports a broad set of ANSI C. It is capable of supporting features such as pointers and dynamic memory allocation. The compiler and its transformations are described in details on this patent [58]. SpecC language by Gajski et al. [48] is a superset of ANSI C that includes many systems and hardware constructs such as FSM, concurrency and pipelining. Although, not all constructs of SpecC are synthesizable, the designer can manually refine the SpecC program into to one that can be. Bach C [59] from Sharp supports explicit concurrency and rendezvous communications. Each operation is sequenced, and arrays are supported but not pointers. C++ can also be used as an HLS language for synthesizing to RTL, some compilers supporting it can even synthesize a subset of SystemC. SystemC is a C++ library that supports hardware and system modeling. An HLS specialized in SystemC is the Cynthesizer from Forte Design System, which was acquired by Cadence in 2014. Cyntheziser supports a strict set of SystemC’s TLM. Calypto’s Catapult C, previously Mentor Graphics, performs a behavioral synthesis from a strict subset of the ANSI C/C++ and SystemC. Vivado HLS, prior AutoESL Autopilot, is one of the most recent HLS tools. Vivado HLS also synthesizes to RTL from C, C++, and SystemC. It is based on the open source LLVM framework, and it uses Clang the LLVM C frontend. As an advantage, with every iteration of LLVM, Vivado HLS naturally retrieves the latest optimizations on LLVM’s compilation techniques. NEC CyberWorkbench targets behavioral synthesis, and it has been used in industry for many years. CyberWorkbench supports BDL [60] and even

2.3. High-Level Synthesis

thought it deviates from C by adding support for I/O ports, specific types and operators, explicit clock cycles and pragmas it can also synthesize C++ and SystemC.

StepNP [61] is a system-level exploration framework based on SystemC targeted at network processors. It enables rapid prototyping and architectural exploration and provides well- defined interfaces between processing cores, co-processors, and communication channels to allow the usage of component models at different levels of abstraction. It enables the creation of multi-processor architectures with models of interconnects (functional channels, NoCs), processors (simple RISC), memories and coprocessors.

BlueSpec [62] takes as input a SystemVerilog or a SystemC subset and manipulates it with technology derived from term rewriting systems (TRS) initially developed at MIT by Arvind et al. It offers an environment to capture successive refinements to an initial high-level design that are guaranteed correct by the system.

CUDA Code FCUDA Annotated code Vivado HLS C Code RTL Design

Annotation Vivado HLS_Synthesis

FPGA Implementation guidelines Coarse-grained Parallelism extraction Fine-grained Parallelism extraction

Figure 2.9 – FCUDA: CUDA to FPGA Flow.

CUDA and OpenCL general purpose GPU development C-like languages have expanded their capabilities for hardware synthesis. FCUDA [63] adapts the CUDA programming model into an FPGA design flow that maps the coarse and fine grained parallelism exposed in CUDA onto the reconfigurable fabric. The primary goal of the FCUDA is to convert thread blocks into C functions, and them use a C-to-gates HLS for synthesis. SOpenCL [64] generates hardware circuits from OpenCL programs as FCUDA does. SOpenCL is based on a source-to-source code transformation step that coarsens the OpenCL fine-grained parallelism into a series of nested loops, and on a template-based hardware generation back-end that configures the accelerator based on the functionality and the application performance and area requirements. Altera’s OpenCL SDK permits the developers to test their algorithms on a personal computers and then, their OpenCL compiler converts the OpenCL program into an FPGA bitstream.

Other programming Languages used for HLS

JHDL or Just Another hardware Description Language [65] is an HLS language that focuses on designing circuits through an object-oriented approach. JHDL synthesizes Java 1.1 without further language extensions. Sea Cucumber [66] is another Java HLS that permits developers

to describe the circuit coarse-level parallelism as concurrent threads. Kiwi [67] is a C# based HLS that accepts the intermediate language output from either .NET or the open source Mono C# compiler and generates Verilog. Pebble [68] is a language for parameterized and reconfigurable hardware design with a simple block-structured syntax. The objective of Pebble is to support development of designs that can be reconfigured in run-time. Esterel [69] is a synchronous programming language for developing systems that react continuously to their environment. UML interface XSM XML -HW platform -Parametrized HW Arcitecture (initial) Mapping (initial) Application Allocation optimization Scheduling Arcitecture (candidate) Mapping (candidate) Schedule (candidate) Mapping Optimized XSM XML Application Model UML Architecture and mapping models UML UML design with

TUT-profile

To dynamic optimization

Figure 2.10 – Koski a UML based Design Flow for HW-SW prototyping.

Unified Modeling Language (UML) is used in software engineering for designing large software programs. A complete design flow using UML for system modeling is achieved by Kukkala et al. and is called Koski, represented in Figure 2.10. The target of the Koski design flow [70] is multiprocessor System-on-Chip (SoC). It is a library based method that hides unnecessary details from high-level design phases but does not require a plethora of model abstractions. The design flow provides an automated path from UML design entry to FPGA prototyping, including functional verification, automated architecture exploration, and back annotation. The design of the architecture is based on the application model: it results in an application specific implementation. Hailpern et al. [71] highlighted that graphical languages are not well accepted because it is slower to use than writing code.