L OS CONFLICTOS TERRITORIALES EN EL M EDIO V INALOPÓ

Grant Martin and Gary Smith on [25] have divided the evolution of High-Level Synthesis into three generation and a primal one. The current generation is the third, and most of the tools are C based (including C++ and SystemC). Late 1970s up until 1980s is the primal period, first generation is from 1980s to 1990s, second generation goes from mid-1990s to early 2000s and the third from early 2000s to today.

The first generation was oriented mainly on data-path research. The second generation, mainly commercial products were driven by high description languages (HDL). Third and current generation follows the trend of C-based HLS oriented on datapath applications. The pioneer tool in "primal" period is the Carnegie-Mellon University design automation or CMU-DA HLS. The design flow is represented in Figure 5.4 and was built by Carnegie Mellon University in the 1970s [26, 27]. Their work focuses on design specification, simulation, and

2.3. High-Level Synthesis

RTL synthesis. Common software code-transformation, which are used by today tools, like dead-code and redundant sub-expression elimination, constant propagation, code motion are used in the synthesis process. The instruction set processor specification (ISPS) language is used as the design specification [28]. The data-memory allocators perform a mapping function from the algorithmic ISPS description to the data-path part of the hardware implementation. Then the module selection binds the abstract components to a database of specified modules and finally a controller of components is produced.

ISP Functional Description

Data-Memory Allocator

Data Path Graph Interconnection Of abstract components

Module Binder

Data Path Graph With Physical Modules Selected

Translation To Sandia Software

Module Data Base TTL

Chips

Sandia Standard

Cells

Figure 2.7 – The CMU design system, one of the earliest HLS.

Although it was a groundbreaking research, this old work had a little impact on the industrial design. This is because large electronics companies were not still using or starting adopting CAD/CAM systems at that period.

During the first generation, a plethora of tools for research and prototyping were built. MI- MOLA [29, 30] a design method with a purpose to produce digital processors from high-level behavioral specification. The design system combines both compiler construction and hard- ware oriented concepts. Advance Design AutoMation or ADAM [31, 32] was a unified frame- work with restricted natural language interface (a dataflow graph representing the behavioral specification) which contained program tools which synthesized RTL designs from behav- ioral descriptions and the prediction tools which guides the designer in exploring the design space. In addition, the Sehwa [33] tool in ADAM can generate pipelined implementations by exploring the design space. The tool is able to synthesize and perform high-level estimates on the area-delay characteristics of designs and to determine the best design that meets the given constraints. Hardware ALlocater or HAL [34] is a data path synthesis tool with three characteristics. Firstly, it offers the analysis of the input data flow graph and attempts to evenly distribute operations with similar resources with a load balancing technique. Secondly, it provides a global pre-selection of operator cells to full fill speed constraints and register and multiplexer optimizations. Finally, HAL proposed a well-known scheduling technique called the force-directed scheduling on [35] and conflict-graph graph coloring technique for sharing resources in the datapath [34]. Flamel [36], a Pascal to gates HLS, extracts parallelism from block-level transformations.

Stack a one-pass transformation on the parse tree that resolves variable/constant unfolding,

conditional assignments, and multiple arguments. This transformation, also provides infor- mation to structural synthesis that minimizes the number of registers. In addition, Hercules introduces an elegant way to handle operations with unbounded delay called relative schedul-

ing [39]. Hyper/Hyper-LP [40, 41] is a high-level synthesis system oriented on power mini-

mization by using architectural and computational transformations. Cathedral/Cathedral-II was specially designed for the synthesis of digital signal processing hardware [42]. In addition, proprietary in-house tools from IBM [43], Philips [44], Motorola [45] were also developed. The second generation started when major EDA companies such as Cadence, Mentor, and Synopsis begun to offer behavioral HDL to RTL synthesis. Most important such as Mentor’s Monet [46] and Cadence’s Visual Architect [47]. In [25] several reasons are highlighted for the failure of the second generation. First it failed to replace the established RTL design because HDL languages were not popular among system designers, and there was a need for a new steep learning curve. In addition, the quality of result were often widely variable and unpredictable, hard to validate result because no verification methods were available at that time, HLS produces poor results for control dominated algorithms, and simulation time were almost as long as RTL synthesis.

Third-generation HLS tools focuses on using C or C-like languages as behavioral descrip- tions. As discussed already on the Introduction chapter, the lack of expressing parallelism with C motivated academics and companies to introduce additional languages extensions and restrictions to make C more compliant to hardware synthesis. In this way, the devel- oper is discouraged to use dynamic structures such as pointers with unknown bounds and recursive functions. Most famous third generations tools are HardwareC [39], SpecC [48], Impulse-C [49], Forte’s Cynthesizer [50] now acquired by Cadence, Calypto’s Catapult [51], NEC Cyber Workbench [52], Synopsis SynphonyC [53] and AutoPilot xPilot acquired by Xilinx and called Vivado HLS [54]. Often tool vendors restrict publications of benchmarking results, but indications shows that third generation HLS tools is achieving reasonable success. In addition, third generation tools are better that the second one because they focus on domain application (Dataflow and DSP design) by achieving reasonable good designs. Furthermore, they provide the "right" input languages that suits more application software developers(eg. C-like and Matlab). Finally, the quality of results are better because HLS can take advantage of compiler-based optimization (Procedural optimization).