HERRAMIENTAS DEL PACIENTE
ABORDAJE DE LAS QUEJAS NO VERBALES O PREVERBALES
The C Box consists of three subunits: the transla tion buffer (TB) , the cache, a nd the NMI i n ter face . Figure 1 is a schematic diagram of this u n i t .
The translation o f a VAX virtual address t o a p h ysi c a l address i s a com p l i ca t e d process . 1 Accesses to system and process page tables are requ ired , and shifting and adding must be done to obtain the final physical address. Performi ng this add ress translation process for every data reference signifi cantly increases the data access time and red uces the read bandwidth. One way
Digital Technical journal
No. 4 Febn�ary 1987
to avoid that is to stare the resul t of this address ca l c u l a t i o n i n a s m a l l , fas t m e m ory c a l l e d a translation b u ffer. Si nce each trans l a t i on can access a page of data ( 5 1 2 bytes in the VAX architecture) , it is likely that the translat ion wil l b e used aga i n i n t h e program being executed . Rather than recalculating the p hys ical address ( PA) on those subsequent accesses, it can be retrieved from the TB.
The translation buffer in the VAX
8800
pro c e s s o r h o l ds 5 1 2 s ys t e m a n d 5 1 2 p rocess ad dress translations. The fol lowing sum marizes the characteristics of the TB .Characteristics of the Translation Buffer
• Direct Ma pped
• 1 024 Lines
- 51 2 System Li nes
- 5 1 2 Process Li nes
• Al location on Translation Buffer Miss
A common approac h to the problem of data access l atency for h igh-speed processors , and the one used in the VAX
8800
CPU, i s tO use a cache 2 A cache is a small , fast memory located between the processor and the m a i n memory system. If the data requested by the CPU is not contained i n the cache , t h a t data is accessed from main memory and loaded i nto the cache.Aspects of the VAX 8800 C Box Design A A B A TB DATA TB TAG TRANSLATION BUFFER TB - TRANSLATION BUFFER VA - VIRTUAL ADDRESS PA - PHYSICAL ADDRESS
A , B - A AND B PHASES OF TWO PHASE CLOCK
B TB DATA CACHE DATA ADDRESS CACHE TAG ADDRESS HIT READ STREAM ADDRESS B U FFERING WRITE STREAM OAT A BUFFERING WRITE BUFFER N M I INTERFACE CACHE N M I
¢:::)
Figure 1 Block Diagram of C Box
Thus . i n the m ajori ty of cases , the cache w i l l c o n ta i n rece n t l y refe r e n c e d d a t a i te m s , a n d future referen ces t o those data i tems w i l l be fetched from the cache. The i ntent is to m i n i mize the number o f longer latency accesses to the main mem ory su bsystem . The success of a cache me mory rel i es on the l oca l i ty of refer· enccs in both time and space .
The data cache i n each VAX 8800 CPU holds 64 kilobytes (KB) of both data and instructions . The list on the right summarizes the characteris tics of the cache .
The TB and the cache are very s i m i lar i n con cept and structure , except that the TB is used to accelerate address translations and the cache tO accelerate data accesses. Eac h consists of a tag section and a data section . The tag section holds the unique identifi e r , or tag, for the data item held in the corresponding data section . The TB and the cache are d irect mapped , meaning that
4 2
Characteristics of the Cache
• Direct Mapped with Physical Address
• Read Al locate Only
• Delayed-Write Cache Update
• Write-through Memory U pdate with Write Buffe ring
• 1 024 Blocks
• 64-byte Block Size
• 4-byte (one longword) Line Size
• 32-byte (one hexword) Cache Refill Size
each a d dress can poi n t to o n l y o n e loca tion ; however, each location can potentia l ly be allo cated to one of many addresses. A tag perm its the identification of a data item i n either the TB or a cache location . The tag in the VAX 8800 processor is an unmodified selection of bits
Digital Technical]ournal
VA(30-1 8) VA(31 -0) TB TB TAG DATA PA(29-0) TB HIT VA - VIRTUAL ADDRESS PA - PHYSICAL ADDRESS TB - TRANSLATION B U FFER PA(29,0) PA(28-16) CACHE PA(1 5-6) DATA CACHE H I T
Figure 2 Translation Buffer and Cache A ddress Mapping
f r o m t h e a d d r e s s of t h e d a t a i t e m b e i n g accessed. This concept is depicted in Figure 2 .
As m e n t i o n e d e a r l i e r , a m e m o ry a c c ess i s r e q u i r e d i f t h e c a c h e d o e s n o t c o n t a i n a requested data item. In the 8800, both proces sors are connected to the memory and the 1/0 subsystems t hrou g h the NMI bus. Al l read and write references that go to these subsystems are processed by the N M I i nterface. This i nterface maintains a set of buffers for both read and wri te reference streams. For the read stream there are actually two sets of address buffers: one for data reads , the other for instruction reads.