Acuerdo de colaboración pesquera entre la UE y Madagascar

data_in <= x"4321" ; addr_bus <= x"FB73" ; qdep <= x"1234" ; ctrl <= x"F" ; rw <= x"F" ;

In this case, processor '0' is requesting memory access within memory block '0' (location '3'), processor '1' within memory block '1' (location '3') , processor '2' within memory block '2' (location '3') and processor '3' within memory block '3' (location '3'). Hence there is no conflict between the processors for memory accesses. Processors '0', '1', '2' and '3' (from 16-bit 'data_in' bus ) are writing '1', '2', '3' and '4' to the corresponding memory locations. As all the processors get the memory access and hence the data '1', '2', '3' and '4' is written to the memory location '3' in each of the four memory blocks. This data can be observed in the corresponding memory locations, on the simulation tracer 1 in Figure 6.4, for ‘scnr’ = ‘0’.

Scenario 1: Input stimulus:

addr_bus <= x"37BF" ; qdep <= x"1234" ; ctrl <= x"F" ; rw <= x"0" ;

In this case, processor '0' is requesting memory access within memory block '3' (location '3'), processor '1' within memory block '2' (location '3') , processor '2' within memory block '1' (location '3') and processor '3' within memory block '0' (location '3'). Hence there is no conflict between the processors for memory accesses. Processors '0', '1', '2' and '3' are reading '4', '3', '2' and '1' from the corresponding memory locations. As all the processors get the memory access and hence the data '4', '3', '2' and '1' is read from to the memory locations 'F', 'B', '7' and '3'. This data can be observed on the ‘data_out’ bus, on the simulation tracer 1 in Figure 6.4, for ‘scnr’ = ‘1’.

Scenarios '0' and '1' test the case of data exchange between processors. In the scenario '0', processor '0' writes '1' to memory location '3' in memory block '0' and processor '3' writes '4' to memory location '3' in memory block '3'. In scenario '1' processor '0' reads '4' (Data written by processor '3' in scenario '0') from memory location '3' in memory block '3' and processor '3' reads '1' (Data written by processor '0' in scenario '0') from memory location '3' in memory block '0'. Similarly data exchange between processors '1' and '2' is also tested.

Scenario 2: Input stimulus: data_in <= x"AAAA" ; addr_bus <= x"CD56" ; qdep <= x"EFFF" ; ctrl <= x"F" ; rw <= x"5" ;

In this case, processor ‘0’ (write) and processor ‘1’ (read) are requesting for memory access within the same memory block '1', but to different memory locations '2' and '1'. Processor ‘1’ gets the access as its processor ID is greater than that of processor ‘0’ and queue depths of the processors is same. So processor ‘1’ reads ‘0’ from the memory location '1' in the memory block '1'. This data is observed on ‘data_out’ bus on the simulation tracer ‘1’ shown in Figure 6.4, for ‘scnr’ = ‘2’. Similarly, processor ‘2’ (for memory write) and processor ‘3’ (for memory read) are requesting for memory access within same memory block '3', but to different memory locations '0' and '1'. Processor ‘2’ gets the access as its queue depth is greater than that of processor ‘3’. So processor ‘2’ writes 'A' to the memory location '1' in the memory block '3'. This data is observed in the memory location ‘D’ on the simulation tracer ‘1’ shown in Figure 6.4, for ‘scnr’ = ‘2’. Scenario 3: Input stimulus: data_in <= x"5555" ; addr_bus <= x"DC65" ; qdep <= x"4434" ; ctrl <= x"F" ; rw <= x"5" ;

In this case, processor ‘0’ (write) and processor ‘1’ (read) are requesting for memory access within same memory block '1', but to different memory locations '1' and '2'. Processor ‘0’ gets the access as its queue depth is greater than that of processor ‘1’. So processor ‘0’ writes ‘5’ to the memory location '1' in the memory block '1'. This data is observed in the memory location ‘5’, on the simulation tracer ‘2’ shown in Figure 6.5, for ‘scnr’ = ‘3’. Similarly, processor ‘2’ (for memory write) and processor ‘3’ (for memory read) are requesting for memory access within same memory block '3', but to different memory locations '0' and '1'. Processor ‘3’ gets the access as its processor ID is greater than that of processor ‘2’ and queue depths of the processors is same. So processor ‘3’ reads 'A' (which was written by processor ‘1’ in the previous scenario) from the memory

location '1' in the memory block '3'. This is observed on ‘data_out’ bus , on the simulation tracer ‘2’ shown in Figure 6.5, for ‘scnr’ = ‘3’.

Scenario 4: Input stimulus: data_in <= x"9999" ; addr_bus <= x"3399" ; qdep <= x"4EE4" ; ctrl <= x"F" ; rw <= x"C" ;

In this case, processor ‘0’ and processor ‘1’ are requesting for memory access (read) with same memory location ‘1’ within same memory block ‘2’. Processor ‘1’ gets the priority as its queue depth is greater than that of processor ‘0’. Hence processor ‘1’ reads ‘0’ (which is reset value) from memory location ‘9’ and is observed on ‘data_out’ bus on the simulation tracer ‘2’, shown in Figure 6.5, for ‘scnr’ = ‘4’. Processor ‘2’ and processor ‘3’ are requesting for memory access (write) with same memory location within same memory block. Processor ‘2’ gets the priority as its queue depth is greater than that of processor ‘3’. Hence processor ‘2’ writes ‘9’ to the memory location ‘3’ in memory block ‘0’. This data is observed in the memory location ‘3’, on the simulation tracer ‘2’ shown in Figure 6.5, for ‘scnr’ = ‘4’.

Scenario 5: Input stimulus: data_in <= x"EEEE" ; addr_bus <= x"7654" ; qdep <= x"5556" ; ctrl <= x"F" ; rw <= x"1" ;

In this case, processor ‘0’ (write), processor ‘1’ (read), processor ‘2’ (read) and processor ‘3’ (read) are requesting for memory access within same memory block ‘1’, but to different memory locations. Processor ‘0’ gets the priority as it has greatest queue depth of all the processors. Hence processor ‘0’ writes 'E' to the memory location '0' in the memory block '1'. This data is observed in the memory location ‘4’, on the simulation tracer ‘2’ shown in Figure 6.5, for ‘scnr’ = ‘5’.

Scenario 6: Input stimulus: data_in <= x"CCCC" ; addr_bus <= x"6666" ; qdep <= x"5555" ; ctrl <= x"E" ; rw <= x"0" ;

In this case, processor ‘1’ (read), processor ‘2’ (read) and processor ‘3’ (read) are requesting for memory access with the same memory location ‘2’ in the memory block ‘1’. Processor ‘3’ gets the priority as its has greatest processor ID of all the processors. Hence processor ‘3’ reads '0' (reset value) from the memory location '2' in the memory block '1', and is observed on ‘data_out’ bus on the simulation tracer ‘3’, shown in Figure 6.6, for ‘scnr’ = ‘6’. Scenario 7: Input stimulus: data_in <= x"FFFF" ; addr_bus <= x"EEAE" ; qdep <= x"0011" ; ctrl <= x"0" ; rw <= x"0" ;

In this case, all processors are in idle state. No transactions are performed through the interconnect. Hence no changes are observed in any of the memory locations or on ‘data_bus’ and are observed on the simulation tracer ‘3’, shown in Figure 6.6, for ‘scnr’ = ‘7’.

The simulation tracers ‘1’, ‘2’ and ‘3’ are shown in Figures 6.4, 6.5 and 6.6 in the next three pages.

The simulation tracers in Figure 6.7 and 6.8 show the behaviour of the interconnect module ‘main_ic’ in different scenarios, which are explained below. In this chapter, the input stimulus and the output of the module ‘main_ic’ under each scenario, observed on the simulation tracers is discussed. (All the data mentioned in different scenarios and that are shown on the simulation tracers are represented in hexadecimal system) Scenario 0: Input stimulus: data_in_prc <= x"4321" ; data_in_mem <= x"FEDC" ; addr_prc <= x"FB73" ; qdep <= x"1234" ; ctrl <= x"F" ; rw <= x"F" ;

In this case, processor '0' is requesting memory access within memory block '0' (location '3'), processor '1' within memory block '1' (location '3') , processor '2' within memory block '2' (location '3') and processor '3' within memory block '3' (location '3'). Hence there is no conflict between the processors for memory accesses and hence 'FLAG' of all the processors is '1'. Processors '0', '1', '2' and '3' are writing '1', '2', '3' and '4'. As all the processors get the memory access and hence the data '1', '2', '3' and '4' (from ‘data_in_prc’ bus) are written to the hexbit (4-bit binary value represented in hexadecimal system) of ‘data_out_mem’ bus corresponding to each memory block, ‘addr_mem’ for each memory blocks gets ‘3’ indicating the location address with in that memory block, ‘rw_mem’ for all memory blocks becomes ‘1’ indicating that it is a memory write operation. This data can be observed on the simulation tracer 4 in Figure 6.7, for ‘addr_prc’ = ‘4321’ and ‘rst’ = ‘0’.

Scenario 1: Input stimulus:

data_in_prc <= x"26FE" ; data_in_mem <= x"FEDC" ; addr_prc <= x"37BF" ; qdep <= x"1234" ; ctrl <= x"F" ; rw <= x"0" ;

In this case, processor '0' is requesting memory access within memory block '3' (location '3'), processor '1' within memory block '2' (location '3') , processor '2' within memory block '1' (location '3') and processor '3' within memory block '0' (location '3'). Hence there is no conflict between the processors for memory accesses. Processors '0', '1', '2' and '3' are reading 'F', 'E', 'D' and 'C' from the ‘data_in_mem’ bus. As all the processors get the memory access and hence the data 'F', 'E', 'D' and 'C' is from the ‘data_in_mem’ bus. This data can be observed on the ‘data_out_prc’ bus, on the simulation tracer 4 in Figure 6.7, for ‘addr_prc’ = ‘37BF’. And ‘addr_mem’ for each memory blocks gets ‘3’ indicating the location address with in that memory block, ‘rw_mem’ for all memory blocks becomes ‘0’ indicating that it is a memory read operation, are also observed.

Scenario 2: Input stimulus: data_in_prc <= x"AAAA" ; data_in_mem <= x"FEDC" ; addr_prc <= x"CD56" ; qdep <= x"EFFF" ; ctrl <= x"F" ; rw <= x"5" ;

In this case, processor ‘0’ (write) and processor ‘1’ (read) are requesting for memory access within same memory block '1', but to different memory locations '2' and '1'. Processor ‘1’ gets the access as its processor ID is greater than that of processor ‘0’

and queue depths of the processors is same. So processor ‘1’ reads ‘D’ from ‘data_in_mem’ bus. This data is observed on ‘data_out_prc’ bus on the simulation tracer ‘4’ shown in Figure 6.7, for ‘addr_prc’ = `CD56’. Similarly, processor ‘2’ (write) and processor ‘3’ (read) are requesting for memory access within same memory block '3', but to different memory locations '0' and '1'. Processor ‘2’ gets the access as its queue depth is greater than that of processor ‘3’. So processor ‘2’ writes 'A' to ‘data_out_mem’ bus to the hexbit corresponding to memory location ‘3’ and the data is observed on ‘data_out_mem’ bus on the simulation tracer ‘4 shown in Figure 6.7, for ‘addr_prc’ = `CD56’. ‘flag’ is ‘1’ for only two processors (processors ‘1’ and ‘2’), ‘addr_mem’ corresponding to memory blocks ‘1’ and ‘3’ becomes ‘1’ indicating the location address with in those memory blocks and ‘rw_mem’ for those locations become ‘0’ and ‘1’ indicating ‘read’ and ‘write’ operation respectively.

Scenario 3: Input stimulus: data_in_prc <= x"5555" ; data_in_mem <= x"FEDC" ; addr_prc <= x"DC65" ; qdep <= x"4434" ; ctrl <= x"F" ; rw <= x"5" ;

In this case, processor ‘0’ (write) and processor ‘1’ (read) are requesting for memory access within same memory block '1', but to different memory locations '1' and '2'. Processor ‘0’ gets the access as its queue depth is greater than that of processor ‘1’. So processor ‘0’ writes ‘5’ to the hexbit on the ‘data_out_mem’ bus corresponding to the memory block '1'. This data is observed on the hexbit on the ‘data_out_mem’ bus corresponding to the memory block, on the simulation tracer ‘4’ shown in Figure 6.7, for ‘addr_prc’ = ‘DC65’. Similarly, processor ‘2’ ( for memory write) and processor ‘3’ (for memory read) are requesting for memory access within same memory block '3', but to different memory locations '0' and '1'. Processor ‘3’ gets the access as its processor ID is

greater than that of processor ‘2’ and queue depths of the processors is same. So processor ‘3’ reads 'F' from hexbit on the ‘data_in_mem’ bus corresponding to memory location ‘3’. This is observed on hexbit on the ‘data_out_prc’ bus corresponding to processor ‘3’, on the simulation tracer ‘4’ shown in Figure 6.7, for ‘addr_prc’ = ‘DC65’. ‘flag’ is ‘1’ for only two processors (processors ‘0’ and ‘3’), ‘addr_mem’ corresponding to memory blocks ‘1’ and ‘3’ becomes ‘1’ indicating the location address with in those memory blocks and ‘rw_mem’ for those locations become ‘1’ and ‘0’ indicating ‘write’ and ‘read’ operation respectively.

Scenario 4: Input stimulus: data_in_prc <= x"9999" ; data_in_mem <= x"FEDC" ; addr_prc <= x"3399" ; qdep <= x"4EE4" ; ctrl <= x"F" ; rw <= x"C" ;

In this case, processor ‘0’ and processor ‘1’ are requesting for memory access (read) with same memory location ‘1’ within same memory block ‘2’. Processor ‘1’ gets the priority as its queue depth is greater than that of processor ‘0’. Hence processor ‘1’ reads ‘E’ from the hexbit on the ‘data_in_mem’ bus corresponding to memory block ‘2’ and is observed on ‘data_out_prc’ bus on the simulation tracer ‘5’, shown in Figure 6.8, for ‘addr_prc’ = ‘3399’. Processor ‘2’ and processor ‘3’ are requesting for memory access (write) with same memory location within same memory block. Processor ‘2’ gets the priority as its queue depth is greater than that of processor ‘3’. Hence processor ‘2’ writes ‘9’ to the hexbit on the ‘data_out_mem’ bus corresponding to the memory block ‘0’. This data is on ‘data_out_mem’ bus on the simulation tracer ‘5’, shown in Figure 6.8, for ‘addr_prc’ = ‘3399’. . ‘flag’ is ‘1’ for only two processors (processors ‘1’ and ‘1’), ‘addr_mem’ corresponding to memory blocks ‘0’ and ‘2’ becomes ‘3’ indicating the

location address with in those memory blocks and ‘rw_mem’ for those locations become ‘1’ and ‘0’ indicating ‘write’ and ‘read’ operation respectively.

Scenario 5: Input stimulus: data_in_prc <= x"EEEE" ; data_in_mem <= x"FEDC" ; addr_prc <= x"7654" ; qdep <= x"5556" ; ctrl <= x"F" ; rw <= x"1" ;

In this case, processor ‘0’ (write), processor ‘1’ (read), processor ‘2’ (read) and processor ‘3’ (read) are requesting for memory access within same memory block ‘1’, but to different memory locations. Processor ‘0’ gets the priority as its has greatest queue depth of all the processors. Hence processor ‘0’ writes 'E' to the hexbit on the ‘data_out_mem’ bus corresponding to the memory block '1'. This data is on the simulation tracer ‘5’ shown in Figure 6.8, for ‘addr_prc’ = ‘7654’. ‘flag’ is ‘1’ for only processor ‘0’, ‘addr_mem’ corresponding to memory block ‘1’ becomes ‘0’ indicating the location address within the memory block and ‘rw_mem’ for those memory blocks become ‘1’ indicating ‘write’ operation.

Scenario 6: Input stimulus: data_in_prc <= x"CCCC" ; data_in_mem <= x"FEDC" ; addr_prc <= x"6666" ; qdep <= x"5555" ; ctrl <= x"E" ; rw <= x"0" ;

In this case, processor ‘1’ (read), processor ‘2’ (read) and processor ‘3’ (read) are requesting for memory access with the same memory location ‘2’ in the memory block ‘1’. Processor ‘3’ gets the priority as its has greatest processor ID of all the processors. Hence processor ‘3’ reads 'D' from the hexbit on the ‘data_in_mem’ bus corresponding to the memory block '1', and is observed on ‘data_out_prc’ bus on the simulation tracer ‘5’, shown in Figure 6.8, for ‘addr_prc’ = ‘6666’. ‘flag’ is ‘1’ for only processor ‘3’, ‘addr_mem’ corresponding to memory block ‘1’ becomes ‘0’ indicating the location address within the memory block and ‘rw_mem’ for those memory blocks become ‘0’ indicating ‘read’ operation.

Scenario 7: Input stimulus: data_in_prc <= x"FFFF" ; data_in_mem <= x"FEDC" ; addr_prc <= x"EEAE" ; qdep <= x"0011" ; ctrl <= x"0" ; rw <= x"0" ;

In this case, all processors are in idle state. No transactions are performed through the interconnect. Hence no changes are observed in any of the memory locations or on ‘data_bus’ and are observed on the simulation tracer ‘5’, shown in Figure 6.8, ‘addr_prc’ = ‘EEAE’.

The simulation tracers ‘4’ and ‘5’ are shown in Figures 6.7 and 6.8 in the next two pages.

The post-implementation simulation tracers shown in Figures 6.4, 6.5 and 6.6 show that the interconnect network module ‘main’, described in Appendix A, experimentally performed correctly from a functional stand-point for all scenarios. The post-implementation simulation tracers shown in Figures 6.7 and 6.8 show that the interconnect network module ‘main_ic’, described in Appendix B, experimentally performed correctly from a functional stand-point for all scenarios that were tested sucessfully on the interconnect module ‘main’.

Chapter 7