CAPITULO IV: RESULTADOS
4.3. RESULTADOS
4.3.1. Análisis de la sentencia del caso “Baguazo” y la protesta social
Xilinx FPGA FOR DC & Stepper MOTOR
FRC FRC1 FRC2 FRC3 FRC4 FRC6 FRC7 Xilinx FPGA
1 74 84 112 122 40 58 FRC FRC9
2 75 85 114 124 41 60 1 7
3 76 86 113 129 42 63 2 5
4 78 87 115 126 48 64 3 3
5 77 93 117 132 50 65 4 141
6 80 94 118 136 51 66 9 5V
7 79 95 121 134 56 67 10 GND
8 83 100 123 139 57 28
9 VCC VCC VCC VCC VCC VCC
10 GND GND GND GND GND GND
FOR LCD & DAC FOR ADC
FRC FRC5 FRC8 FRC10
1 4 96 62
2 20 99 59
3 19 101 49
4 21 102 47
5 23 103 46
6 22 116 4
7 26 120 43
8 27 131 13
9 30 133 12
10 29 137 11
11 31 138 10
12 38 140 6
13 5V 5V 5V
14 -5v -5v -5v
15 3.3 3.3 3.3
16 GND GND GND
POSSIBLE VIVA QUESTION & ANSWER 1. What is HDL?
Hardware description language is a computer aided design(CAD). Tool to design and synthesis of digital system. HDL language is similar to language.
2. HDL language is similar to which language?
It is similar to C Language.
3. Justify the statement "Debugging the design is easy " in HDL.
Yes, because HDL packages implementation simulator & test benches 4. List the Hardware Description Language?
VHDL & Verilog
5. What is the abbreviation of VHDL?
VHDL means Very High Speed Integrated Circuit(VHSIC) hardware description language.
6. What is the VHDL standard ?
The updated standard in 1993 is IEEE standard 1076-1993.
7. Write the general structure of VHDL model?
entity entity_name is
port(define input and output port);
architecture architecture_name is begin
statements;
end architecture_name;
8. Write the general structure for verilog?
module modulename(input and output variable);
input...;
output...;
statement;
endmodule;
9. Which package is attached with VHDL program?
std_logic_1164 package is attached with VHDL program.
10. What is the Verilog HDL standard and who is maintaining it?
IEEE standard 1364-1995 is the verilog HDL standard and it is maintain by verilog international organization.
11. In VHDL, what are the modes that the ports can take?
in, out, buffer, inout.
12. Explain the function of the modes of the port.
in-The port is only an i/p and appears only on the right hand side of the statement.
out-The port is only an o/p and appears only on the left and right hand side of the statement.
buffer-The port can be used as both i/p & o/p but should have only one source.
inout-The port can be used as both an i/p & o/p.
13. Explain the structure of the verilog module.
The verilog module has two parts, Declaration & Body.
Declaration- name, inputs and outputs of the module are listed.
Body-shows the relationship between the inputs & outputs.
14. Which of two Hardware Description Language is case Sensitive?
Verilog is case Sensitive.
15. How should the module be terminated in verilog?
The module is terminated by the predefined word end module.
16. What are the modes that exists in verilog ports?
input : The port is only an i/p Port.
output : The port is only an o/p Port.
inout : The port can be used as both an i/p and o/p.
17. How are the operators broadly classified?
Logical- AND,OR,XOR.
Relational =,=,<,<,>,>
Arithmetic +,-,*,
Shift to move the bits of an objects in a certain direction right or left.
18. State the different types of Logical Operators.
Logical Operators are AND, OR, NAND, NOR, NOT and Exclusive-OR.
19. Write the verilog bitwise logical operators.
AND - &, OR - |, NAND - ~(&), NOR - ~(|), EX-OR - ^, EX-NOR - ~ ^, NOT- ~.
20. What are Boolean Logical Operators, Give example.
The Boolean Logical operators operate on 2 operands, the result is Boolean 0 or 1.
Verilog Boolean logical operators are &&-AND Operator, ||-OR Operator.
21. What are Reduction Operators. Give examples.
The Reduction Opetators operate on a single Operand and the result is Boolean.
Example of verilog Reduction Logical Operators are:
& Reduction AND | Reduction OR ~& Reduction NAND
~| Reduction NOR
^ Reduction XOR
~ ^ Reduction XNOR
! Negation.
22. What are relational Operators. Give example.
Relational Operators are used to compare the values of two objects and the result is Boolean 0 or 1, the VHDL relational operators are:
= Equality /= Inequality < Less than
<= Less than or equal > Greater than
>= Greater than or equal.
23. What are Arithmetic Operators. State few arithmetic Operators in HDL?
Arithmetic Operators performs various operators like.
VHDL Arithmetic Operators Verilog Arithmetic Operators
24. What are shift & rotate operators?
Shift Left represents multiplication by 2.
Shift Right represents division by 2.
25. What are the different types of VHDL data types?
The VHDL data types are broadly classified into 5 types.
Unsigned
26. What are the different types of data types in Verilog?
Nets, Registers, Vectors, Integers, Parameters, Real, Array.
27. What are the different styles of writing the description?
Behavioral, Structural, Switch level, Data flow, Mixed language.
28. What is Behavioral Description?
Behavioral description models the system as to how the o/p's behave with the i/p's. In behavioral description the architecture includes predefined word process in VHDL and always/initial Verilog module.
29. What is Structural Description?
Structural description model the system as component or gates.
Key word component is used in the architecture(VHDL) if gate construct.
In Verilog and, or, not is included in the module.
30. Explain what is Switch level description?
The system is described using switches or transistors. The verilog key words nmos, pmos, cmos, transistors describes the system.
31. Explain what is data flow?
The data flow describes how the systems signal flows from the inputs to the outputs. The description is done by writing the Boolean functions of the outputs.
32. What are the advantages of using mixed type description?
Mixed type description use more than one type or style of the previously mentioned descriptions.
33. What is the function of data flow descriptions?
Data flow descriptions simulates the system by showing how the signa flows system inputs to outputs.
34. How is signal assignment done in HDL?
In VHDL the signal assignment operator <= is used & in verilog, the predefined word assign is used.
35. How do you declare a constant in HDL?
A constant is VHDL is declared by using the predefined word constant and in verilog it is declared by its type like time or integer.
To assign a value to a constant assignment operator :=is used in VHDL & = in verilog.
36. Write a time delay signed assignment statement.
To assign a delay time to a signed - assigned statement the predefined word after is used in VHDL & in Verilog it is # (Delay time).
Ex : S1 - sel and b after 10 nsec - VHDL.
assign # 10 S1=sel & b // Verilog.
37. Define Vector data types.
A vector is a data type that declares an array of similar elements such as to declare an object that has a width of more than 1 bit.
38. What is the difference between syntax error and semantic error?
Syntax error is those that result from not following the rules of the language. it terminates compilation of the program.
A semantic error is an error in the mechanics of the statement. it may not terminate the program, but the outcome of the program may not be as expected.
39. What is the function of Behavioral Description?
The behavioral description describes the system by showing how the outputs behave according to changes in its inputs. In behavioral description one need not know the logic diagram of the system but one should know how the output behaves in response to change in the output.
40. What are the two phase of execution in HDL?
The two phases of execution in HDL are Calculation and Assignment.
41. What do you mean by Sequential Calculation?
Sequential calculation means the calculation of a statement will not wait until the proceeding statement is assigned only until the calculation is done.
42. Which are the Sequential statements that are assigned with behavioral description?
If statement, else-if, loop statements, for loop, forever, report, repeat, next-exit.
43. State the difference between signal and variable assignment.
A process is written based on signal assignment statements and then another process is written based on variable assignment statements. The difference can be observed by the simulation wave forms.
44. When do use loop statements and what is its advantage?
Loops is used to repeat the execution of statements written inside the body. The number of repetitions is controlled by the range of an index parameter. The loop allows the code to be shortened.
45. When is Structural Description best suited?
It is best suited when the digital logic of the system hardware components is known.
46. What type of components are used in structural description?
Components can be gate level: AND, OR, NOT, XOR, XNOR gates. Components can be of higher logic level such as Register Transfer Level (RTL) or processor level.
47. What type of statements are written in Structural Description and why?
Statements are “Concurrent “ in nature. At any simulation time, all statements that have an event are executed concurrently.
48. Difference between VHDL & Verilog structural description.
Verilog recognizes all the primitive gates such as AND, OR, NOT, XOR, XNOR. Basic VHDL packages do not recognize any gates unless the package is limited to one more libraries, packages that have gate description.
49. List the verilog built-in gates.
BUFFER, NOT, AND, NAND, OR, NOR, XOR, XNOR.
50. Does VHDL have built-in gates.
No, VHDL does not have built-in gates.
51. What is Binding?
Binding is linking segment 1 in the code to segment 2 in the same code which makes information in segment 2 visible to segment 1.
52. Types of Bindings performed.
(i) Binding between Entry and component in VHDL (ii) Binding between library and module in VHDL.
(iii) Binding between library and component in VHDL.
(iv) Binding between two modules in verilog.
53. What are State Machines?
Synchronous sequential circuits are called “State Machines”.
54. What are the main components of State Machines.
Latches and Flip Flops. Additional combinational components may also be present.
55. Which are the two types of synchronous Sequential Circuits.
Mealy and Moore Circuits.
56. What is a Mealy Circuit?
The output or next state of Mealy circuit depends on the inputs and the present state of flip flops/latches.
57. What is Moore Circuit?
The output or next state of Moore circuit depends only on the present state. Present and next states for particular flip-flops are the same output pin.
58. Define state diagram.
A diagram which shows transition between states.
59. What is a ‘Generate’ statement?
It is mainly used for repetition of concurrent statement.
60. Name the keyword used to define global constants in VHDL and Verilog.
Generic in VHDL and parameter in Verilog.
61. Disadvantage of structural description in VHDL.
(i) Structural description VHDL code looks much longer than the Verilog
code as it dose not have built-in libraries or packages for logical gates.
(ii) The description is not suited when the number of gates becomes larger.
62. What is Switch Level Description?
Switch Level Description implements Switches (transistors) to describe relatively small-scale digital systems.
63. Application Area of Switch level description.
Very Large Scale Integrated (VLSI) Circuit layouts.
64. Disadvantages of Switch Level description.
(i) Only small-scale systems can be simulated using pure switch level description.
(ii) If the system is not small, huge number of switches are needed that may render simulation impractical.
65. Are built-in-switches statements present in Verilog. If Yes? What are they?
Yes. They are Nmos, Pmos and Cmos.
66. Built-in Switches statement present in VHDL?
No, but to use these statements, user built packages must be developed.
67. What are strong Outputs?
The o/p is either the ground or the Vdd.
68. What is pmos Switches?
For a strong signal it should Pass1.
69. What is nmos Switches?
For a strong signal it should Pass0.
70. What is cmos Switches?
The Switch which can pass both strong 1 and strong 0 is a Cmos Switch.
71. What are Bi-directional Switches?
Bi-directional Switches conduct in both ways from drain to source from source to drain.
72. Application of Bi-directional Switches Used as Bi-directional buffer(bunes).
73. List the three types of Bi-directional switches in Verilog.
Tran, Tranif 0, Tranif 1.
74. Operation of three types of Bi-directional Switches.
(i) Switch ‘Tran’ has no control. It conducts all the time.
(ii) Switch ‘Tranif 1’ conducts if control is 1,otherwise the o/p is put on high impedance.
(iii) Switch ‘Tranif 0’ conducts if control is 0,otherwise the o/p is put on
High impedance.
75. What is a procedure Task and functions?
Procedure and task can have more than one i/p and more than o/p, function have a single o/p,but can have more than one i/p.
76. Where do procedures and functions exits in VHDL?
They can be called only from within the ‘Process’.
77. Where do Task and functions exits in Verilog?
Task and function in Verilog can be called only from within ‘always’
or ‘initial’.
78. Define task.
Task are Verilog sub programs.
79. Define Procedure.
Procedure are VHDL sub programs.
80. Define Functions.
Functions are behavioural statements which must be called inside process for VHDL or always or initial for Verilog.
81. Advantages of using Functions,Procedures,Tasks.
(i) They optimize the style of writing HDL Code.
(ii) They shorten the code.
82. Difference between VHDL and Verilog with reference to pocedure.
VHDL allows procedure calls to be written inside functions. Verilog does not allow such calls.
83. List some of the functions available in VHDL packages.
(i) Mod : Finds modulesof X mod Y.
(ii) Abs : Finds the absolute value of a signed number.
(iii) To-INTEGER : Which return an integer value of a signed input.
(iv) To-INTEGER : Which takes an integer and returns its signed binary equivalents.
84. List the main characteristics of Procedures, Tasks and Functions.
The body of the procedure cannot include behavioural statement 'Process'.
The body of the task cannot include 'Always' or 'Initial', functions return a single output with 'Return', a predefined word.
85. What is the necessity of Mixed - Type Description?
For best implementation of code in both behavioral and structural description.
Explanation with examples.
86. Mention some VHDL Pre-defined types.
Bit, Std_logic, array and natural.
87. Give few examples of User-Defined types.
Week days, weather or grades or classes.
88. Which is Pre-defined word used to instantiate a user defined types?
Type; Ex : Type week days is (Mon, Tue,Fri);
89. Explain this statement. Signal Scores.
Grades declares signal scores as of the type grades.
90. What is the advantage of Packages?
Packages allow the usesd to access built-in constructs.
91. Write Syntax for Package.
Package<Package Name>is End<Package name>
Package body <Package name>is --- End <Package name>
92. What is described in the body of the package?
The body of the packages contains the code for all the identifiers listed in the declaration.
93. Tone/Falls: VHDL allows for multi dimensional arrays but Verilog only allows single dimensional arrays.
94. Write VHDL syntax for single dimensional array.
Type data vector is array(3 downto 0) of word array;
Sub type word array is Std_Logic_Vector(1 downto 0).
95. Give Syntax for verilog single dimensional array.
Reg[1:0] data vector[0:3]
96. Mention the Pre-defined object type to declare the file.
File.
97. What is Port Direction?
Port Direction or mode of the file is nothing but the purpose of file i.e. input file or output file. They are declared as infile or outfile.
98. What is Textio?
It is an IEEE packages used with the file handling programs.
99. Mention the built-in procedures for file handling?
File- open, read line, write line, read, write, and file_close.
100. Give an Example for implementation of File- Open.
File_Open (F Status, infile, “testfile.txt”, read_mode);
101. Write syntax to open a text outfile by t e name of HDL.txt?
File_Open (F Status, outfile, “HDL.txt”, write_mode);
102. What is Write line?
Write Line is Pre-Defined procedure that writes a line into an outfile that is open for write mode.
Ex: Writeline(outfile, temp)
103. Mention the Built-in tasks for accessing a file Verilog?
$fopen, $fdisplay, $fmonitor, $fclose.
104. Explain the statement $monitor(ch1,”%”,quantity);
The above task monitors the variable quantity and records its value in binary in the file testfile.txt, indicator by Ch1;
105. Give Escape characters which can be used with monitor statement?
\ n, \t, \\, \”,\.
106. What is Record type?
Record type is a collection of elements, the elements of which can be of the same type or different types.
107. Why Mixed – Language Description?
Mixed Language description can combine the advantages of both VHDL and verilog in one module.
For example : VHDL has more – Extensive file operations than verilog, including write and read. By writing mixed – language, we can use the VHDL file operations in verilog module.
108. What are the Limitations of Mixed – Language Descriptions?
1. Not all VHDL data types are supported in MLD.
2. The VHDL port type buffer is not supported.
3. Only a VHDL components constructs can invoke a Verilog module. We cannot invoke a verilog module from any other construct in the VHDL Module.
109. Which data types of VHDL are supported for MLD?
Bit, Bit_Vector. Std_logic, Std_ulogic _vector and Std_ulogic_vector.
110. Is it possible to invoke procedure or function by verilog module?
No, A Verilog module can only invoke VHDL entity.
111. What is Synthesis?
Synthesis maps between the simulation (Software) domain and the hardware domain.
112. What information is carried from Entity and Module?
Provides informations on i/ps and o/ps and their types.
113. Write the Entity for figure1
Entity system is
port(a, b: in unsigned(3 downto 0);
d: out integer range(-10 to 10));
end system;
114. Write the Verilog code for figure2
always @(x) begin y = x;
end endmodule
115. Write the Verilog code for figure3 always @(a, x)
begin if(a==1’b1) y=x;
else y=1’b0;
end
QUESTION BANK
1a. Write and execute an VHDL / Verilog code to realize all logic gates and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.
2a. Write and execute an VHDL / Verilog code to realize 2:4 decoder and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to display message on the given seven segment displays accepting Hex key pad input data.
3a. Write and execute an VHDL / Verilog code to realize 8:3 encoder and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different frequency.
4a. Write and execute an VHDL / Verilog code to realize 8:1 MUX and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different frequency.
5a. Write and execute an VHDL / Verilog code to realize 4-bit Binary to Gray code converter and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of Stepper Motor.
6a. Write and execute an VHDL / Verilog code to realize 1:8 DEMUX and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate triangular waveform using DAC.
7a. Write and execute an VHDL / Verilog code to realize N bit comparator and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.
8a. Write and execute an VHDL / Verilog code to realize Full Adder using Behavioral modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the external lights using relays.
9a. Write and execute an VHDL / Verilog code to realize Full Adder using Structural modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.
b. Write and execute an VHDL code the external lights using relays.