CAPITULO II: MARCO TEÓRICO
2.2. BASES TEÓRICAS
2.2.3. Rol del juez
Operation Opcode A B Zout
A+B 000 1111 0000 00001111
A-B 001 1110 0010 00001100
A or B 010 1111 1000 00001111
A and B 011 1001 1000 00001000
Not A 100 1111 0000 11110000
A1*B1 101 1111 1111 11100001
A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100
VHDL CODE VERILOG CODE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alunew1 is
Port( a1,b1:in std_logic_vector(3 downto 0);
opcode : in std_logic_vector(2 downto 0);
zout : out std_logic_vector(7 downto 0));
end alunew1;
architecture Behavioral of alunew1 is
signal a: std_logic_vector( 7 downto 0);
signal b: std_logic_vector( 7 downto 0);
begin
a<= "0000" & a1;
b<= "0000" & b1;
zout<= a+b when opcode ="000" else a-b when opcode ="001" else a or b when opcode ="010" else a and b when opcode ="011" else not a when opcode ="100" else a1 * b1 when opcode ="101" else
module ALU ( a, b, s, en, y );
input signal [3:0]a, b;
input [3:0]s;
a nand b when opcode ="110" else a xor b;
end Behavioral;
Simulation Result Before Execution
After Execution
EXPERIMENT 6
AIM:Develop the HDL code for the following flip-flop: SR, JK, T, D.
COMPONENTS REQUIRED:FPGA board, FRC’s and power supply.
THEORY :
SR flip-flop: A SR flip - flop is the simplest possible memory element. The SR flip flop has two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.
D flip-flop: This is a flip - flop with a delay (D) equal to exactly equal to one cycle of the clock. The defect with SR FF is the indeterminate output when the data inputs at S and R are 1. In order to avoid this the input to R is through an inverter from S so that the input to R is always the complement of S and never same. The S input is redesignated as D.
JK flip-flop: The JK flip flop is called a “universal flip flop” because the other flip flops like D, SR, T can be derived from it. The “racing or race around condition” takes place in a JK FF when J=1 and K=1 and clock=1.
T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and K.
a. SR FLIP FLOP
Block Diagram
Truth Table
clk
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SR_ff is
port ( clk, s, r : in std_logic;
q : buffer std_logic);
end SR_ff;
architecture Behavioral of SR_ff is begin
process( clk) begin
if (clk'event and clk = '1') then if (s='0' and r='0')then q<= q;
module srff(sr, clk, q, qb);
input [1:0] sr;
After Simulation
User Constraint File
net “s” loc = “p74”;
net “r” loc = “p75”;
net “clk” loc = “p18”;
net “q” loc = “p84”;
b. JK FLIP FLOP
Block Diagram
Truth Table
j
k q
Rst Clk J K Q Qb
1 1 0 0 Previous state
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Qb Q
1 No +ve edge - - Previous state
0 - - - 0 1
JK FF
clk qb rst
VHDL CODE VERILOG
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jk_ff is
port ( clk : in std_logic;
jk : in std_logic_vector(1 downto 0);
q, qb : out std_logic);
end jk_ff;
architecture Behavioral of jk_ff is begin
process(clk)
variable temp1, temp2 : std_logic;
begin
if rising_edge(clk) then case jk is
when "01"=> temp1 :='0';
when "10"=> temp1 :='1';
when "00"=> temp1 := temp1;
when "11"=>temp1 := not temp1;
when others => null;
module jkff(jk, clk, q, qb);
input [1:0]jk;
After Simulation
User Constraint File
net “jk<1>” loc = “p75”;
net “jk<0>” loc = “p76”;
net “clk” loc = “p18”;
net “q” loc = “p84”;
net “qb” loc = “p85”;
c. T FLIP FLOP
Block Diagram
Truth Table
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tff is
port ( t, clk : in std_logic;
q : buffer std_logic);
end tff;
architecture Behavioral of tff is begin
process(clk) begin
if (clk’event and clk=’1’)then q <= not t;
1 x No +ve edge Previous state
0 x x 0
T ff
User Constraint File
net “t” loc = “p74”;
net “clk” loc = “p18”;
net “q” loc = “p84”;
d. D FLIP FLOP
Block Diagram
Truth Table
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
architecture Behavioral of dff is begin
User Constraint File
net “d” loc = “p74”;
net “clk” loc = “p18”;
net “q” loc = “p84”;
EXPERIMENT 7
AIM:Design 4 bit Binary, BCD counter (Synchronous reset and Asynchronous reset and any sequence counters.
COMPONENTS REQUIRED:FPGA board, FRC’s and power supply.
a)BCD COUNTER
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
architecture Behavioral of bcd is
signal clkd:std_logic_vector(21 downto 0);
else if(dir==0 & q==4'd15) begin
temp:=temp+1;
elsif(dir='0') then temp:=temp-1;
end if;
if(dir='1' and temp="1010") then temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;
end Behavioral;
User Constraint File
net “clk” loc = “p18”;
net “clr” loc = “p74”;
net “q<0>” loc = “p84”;
net “q<1>” loc = “p85”;
net “q<2>” loc = “p86”;
net “q<3>” loc = “p87”;
b. BINARY COUNTER(Synchronous counter)
Block Diagram
Truth Table
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bin_as is
port ( rst, clk : in std_logic;
q : out std_logic_vector (3 downto 0));
end bin_as;
architecture Behavioral of bin_as is
signal temp : std_logic_vector(3 downto 0);
signal clkd : std_logic_vector(21 downto 0);
signal clkdiv : std_logic;
if clk= ‘1’ and clk’ event then if rst = ‘1’ then
end if;
end if;
q<=temp;
end process;
end Behavioral;
User Constraint File
net “clk” loc = “p18”;
net “rst” loc = “p74”;
net “q<0>” loc = “p84”;
net “q<1>” loc = “p85”;
net “q<2>” loc = “p86”;
net “q<3>” loc = “p87”;
c. BINARY COUNTER(ASynchronous counter)
VHDL CODE library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity asy is
port ( rst, clk : in std_logic;
q : out std_logic_vector (3 downto 0));
end asy;
architecture Behavioral of asy is
signal temp : std_logic_vector(3 downto 0);
signal clkd : std_logic_vector(21 downto 0);
signal clkdiv : std_logic;
begin process(clk) begin
if clk = ‘1’ and clk’ event then clkd<= clkd + '1';
end if;
end process;
clkdiv<= clkd(21);
process(clkd, rst) begin
if rst = ‘1’ then
temp<=(others =>’0’);
elsif clk = ‘1’ and clk’ event then temp <= temp + ‘1’;
q<=temp;
end if;
end process;
end Behavioral;
User Constraint File
net “clk” loc = “p18”;
net “rst” loc = “p74”;
net “q<0>” loc = “p84”;
net “q<1>” loc = “p85”;
net “q<2>” loc = “p86”;
net “q<3>” loc = “p87”;