ANALISIS DE RESULTADO, EVALUACIÓN Y SEGUIMIENTO

The TDC is implemented on chip in 130 nm standard CMOS technology operating at 1.5 V (Fig. 18). The core area of the chip is 0.8 mm ×0.8 mm. Table 3 gives an overview of the measured performance of the chip. Figure 19 shows the linear- ity of the time measurement for a operation frequency of 350 MHz with minimal time resolution. The plot is generated by applying a square wave at 1/8th of the clock frequency and by sweeping the skew between the input and the clock signal. From the measurements, the clock period relative to the resolution can be derived by taking the difference between m1and m2, which equals to 47 delay units. This

corresponds to a time resolution of 61 ps. The DNL and INL is within+/−1 LSB over the whole measurement range. Figure 20 shows that the jitter of the delay line is equal to 4.2 ps, well within 1 LSB. A power consumption of 25 mW is measured. DECOUPLING INPUT DRIVER TDC + DTC

Fig. 18 Picture of the TDC chip layout. The core TDC circuit measures 0.8 mm×0.8 mm

Table 3 Measured chip performance

Operation frequency 350 MHz

Measured resolution 61 ps

RMS jitter delayline 4.2 ps

Maximum INL +/–1 LSB

Power consumption 25 mW

−10000 −500 0 500 1000 1500 2000 2500 50 100 time difference (ps) TDC o u tp u t (risin g ) −10000 −500 0 500 1000 1500 2000 2500 50 100 time difference (ps) TDC o u tp u t (fallin g ) 0 5 10 15 20 25 30 35 40 0.5 1 1.5 2 2.5 m1 (code) time delay (ns) 5 10 15 20 25 30 35 40 −1 1 m1 (code) DNL (LSB) 5 10 15 20 25 30 35 40 −1 1 m1 (code) INL (LSB) m2 m2 m1 m1

Fig. 19 Sweep over the whole measurement range and the non-linearity of the TDC

5 Conclusion

In this paper, a new scheme for a fully-digital CDR circuit is proposed which com- bines immediate acquisition with a continuous frequency range. It uses a TDC that measures the time location of the incoming data edges. This time information is passed to a decision block which extracts the clock and data information. A wave- form generator is then used to reconstruct the original data and a synchronized clock. Since the TDC can immediately and precisely measure every data edge, synchro- nization is obtained instantaneously. Also because there is no relation between the TDC reference clock and the incoming data rate, the frequency range is theoretically

Fig. 20 Jitter plot of the output of the delay line

infinite up to the reference frequency. The precision of this CDR scales with technology and is therefore especially profitable in deep submicron technologies with increasing accuracy and decreasing power consumption compared with analog alternatives.

Also a design example of a prototype TDC in 0.13␮m CMOS technology is presented. It operates at frequencies up to 500 MHz with a time resolution in the range between 50 and 150 ps. It can handle a continuous range of data rates up to the clock frequency. Measurements show 61 ps resolution with 4.2 ps jitter for a 350 MHz operation frequency, consuming 25 mW.

References

1. Jansson, J.-P., Mantyniemi, A., Kostamovaara, J., “A CMOS time-to-digital converter with better than 10 ps single-shot precision,” Solid-State Circuits, IEEE Journal, vol.41, no.6, pp. 1286–1296, June 2006.

2. Steyaert, M., Peluso, V., Bastos, J., Kinget, P., Sansen, W. “Custom analog low power design: The problem of low voltage and mismatch,” 1997 IEEE Custom Integrated Circuits Confer-

ence, pp. 285–292, May 1997.

3. Bult, K. “Analog design in deep sub-micron CMOS,” Proceedings of the 26th European Solid-

State Circuits Conference, September 2000.

4. Daniels, J., Dehaene, W., Steyaert M., Wiesbauer, A., “A/D Conversion Using an Asyn- chronous Delta-Sigma Modulator and a Time-to-Digital Converter,” International Symposium

on Circuits and Systems, May 2008.

5. Staszewski, R.B., Vemulapalli, S., Vallur, P.; Wallberg, J.; Balsara, P.T., “1.3 V 20 ps time-to- digital converter for frequency synthesis in 90-nm CMOS,” Circuits and Systems II: Express

Briefs, IEEE Transactions, vol.53, no.3, pp. 220–224, March 2006.

6. Staszewski, R.B., Wallberg, J.L., Rezeq, S., Chih-Ming H., Eliezer, O.E.. Vemulapalli, S.K., Fernando, C., Maggio, K., Staszewski, R., Barton, N., Meng-Chang L., Cruise, P.,

Entezari, M., Muhammad, K., Leipold, D., “All-digital PLL and transmitter for mobile phones,” Solid-State Circuits, IEEE Journal, vol. 40, no. 12, pp. 2469–2482, Dec. 2005. 7. Staszewski R.B., Balsara, P.T., “All-Digital PLL With Ultra Fast Settling,” Circuits and Sys-

tems II: Express Briefs, IEEE Transactions, vol. 54, no. 2, pp. 181–185, Feb. 2007.

8. Kratyuk, V., Hanumolu, P.K., Moon, U.-K, Mayaram, K., “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” Circuits and

Systems II: Express Briefs, IEEE Transactions, vol. 54, no. 3, pp. 247–251, March 2007.

9. Henzler, S., Koeppe, S., Lorenz, D., Kamp, W., Kuenemund, R., Schmitt-Landsiedel, D., “Variation tolerant high resolution and low latency time-to-digital converter,” 33rd European

Solid State Circuits Conference, 2007. ESSCIRC, vol., no., pp. 194–197, 11–13 Sept. 2007.

10. Dudek, P. et al., “A high-resolution CMOS time-to-digital converter utilizing a vernier delay line,” Transactions on Solid-State Circuits, vol. 35, no. 2, 2000.

11. Chen, P., Liu, S.-L., Wu, J., “A CMOS pulse-shrinking delay element for time interval mea- surement ,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transac-

tions, vol. 47, no. 9, pp. 954–958, September 2000.

12. Mota, M., Christiansen, J., “A high-resolution time interpolator based on a delay locked loop and an RC delay line,” Solid-State Circuits, IEEE Journal, vol. 34, no. 10, pp. 1360–1366, October 1999.

13. Nutt, R. “Digital time intervalometer,” The Review of Scientific Instruments vol. 39, pp. 1342, 1968.

14. Gardner, F., “Charge-pump phase-lock loops,” IEEE Transaction Communication, vol. COM- 28, no. 11, pp. 1849–1858, November 1980.

15. Nakamura, M., Ishihara, N., Akazawa, Y., “A 156 Mbps CMOS Clock Recovery Circuit for Burst-mode Transmission,” Symp. VLSI Circuits, pp. 122–123, June 1996.

16. Nogawa, M., Nishimura, K., Kimura, S., Yoshida, T., Kawamura, T., Togashi, M., Kumozaki, K., Ohtomo, Y., “A 10 Gb/s burst-mode CDR IC in 0.13/spl mu/m CMOS,” Solid-State Cir-

cuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, vol.,

no., pp. 228–595 Vol. 1, 10-10 Feb. 2005.

17. Kobayashi, S., Hashimoto, M., “A multibitrate burst-mode CDR circuit with bit-rate discrim- ination function from 52 to 1244 Mb/s,” Photonics Technology Letters, IEEE, vol. 13, no. 11, pp. 1221–1223, November 2001.

18. Yang, C.-K.K., Farjad-Rad, R., Horowitz, M.A., “A 0.5−␮m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling,” Solid-State Circuits, IEEE Journal, vol. 33, no. 5, pp. 713–722, May 1998.

19. Ahmed, S.I., Kwasniewski, T.A., “Overview of oversampling clock and data recovery circuits,” Electrical and Computer Engineering, 2005. Canadian Conference, vol., no., pp. 1876–1881, 1–4 May 2005.