CALIBRACIÓN DEL MODELO

the package to the PCB.

Attachment of the Die to the Package.

Figure 5.7 depicts two of the most common methods of die attachment. Although many other techniques exist, these are by far the most common. First, let's explore the wire bond

method of attaching the chip to the package. This is probably the most widely used method. A wire bond is simply a very small wire with a diameter on the order of 1 mil. Just for reference, the diameter of a human hair is approximately 3 mils. The primary impact of a bond wire is added series inductance. Bond wire lengths vary from approximately 50 to 500 mils. Since bond wires are so short, they are often modeled as a discrete inductor. There are several methods of obtaining the equivalent inductance of a bond wire. Equation (5.3) can be used as a quick approximation; however, the most accurate means

Figure 5.7: Common methods of die attachment: (a) wire bond attachment; (b) flip chip

Figure 5.8: Modeling the arch of a bond wire.

of bond wire inductance calculation requires that the arch of the bond wire and the proximity of the ground plane be accounted for. If there is no local ground or power plane, equation (5.3) is an excellent approximation. However, if the wire passes over a plane, it is necessary to account for the arch and the height above the plane. Figure 5.8 depicts the best way to do this. This particular example divides the bond wire into four sections. The first section, A, is roughly perpendicular to the reference plane; subsequently, the reference plane will have a minimal effect and its contribution to the inductance can be calculated with equation (5.3). Section B is roughly parallel to the reference plane with an approximate height of H1.

Subsequently, the inductance LB must be calculated using the inductance of a straight wire

in the presence of a ground plane [Johnson and Graham, 1993]: (5.12)

where l is the length in inches, h the height above the ground plane, and d the wire diameter.

LC must be calculated in the same manner as LB using a height of H2. LD is calculated using

equation (5.3) because it is roughly perpendicular to the reference plane. To gain better accuracy, a two-dimensional field simulator should be used to calculate the inductance of each section instead of the equation presented here. A three-dimensional simulator would allow a more exact inductance calculation; however, it is usually not worth the extra effort because the radius of the arch will change for each bond wire. Subsequently, any additional accuracy gained from the use of a three-dimensional simulator would be negated by the fact that it is impossible to quantify the exact physical characteristics of each bond wire in the system.

Wire bonds also exhibit a large amount of crosstalk, which will cause pattern-dependent inductance values and ground return path problems that will be governed by equations (5.6) through (5.11). If there is no local ground plane, equation (5.5) can be used to estimate the mutual inductance between two bond wires. Otherwise, the following equation should be used to approximate the effect of a local ground plane [Johnson and Graham, 1993]:

(5.13)

where L is the self-inductance of the two bond wires, s the center-to-center spacing, and h the height above the ground plane. A field solver should be used, however, to obtain the most accurate results. Furthermore, bond wires will tend to exacerbate rail collapse and simultaneous switching noise, which we explore in Chapter 6.

Although the use of bond wires leads to increased inductance and reduced signal integrity, the advantage is that they are inexpensive, mechanically simple, and allow for some changes in the bonding pad location and package routing. Furthermore, since the back of the chip is attached directly to the package substrate, it allows maximum surface area contact between the die and the package, which maximizes heat transfer out of the die. Additionally, when using bond wires, the I/O pads tend to be limited to the periphery of the die, which will inflate the die size for a large number of I/O.

Now let's consider flip-chip technology. Essentially, it is almost ideal from an electrical point of view. A flip-chip connection is obtained by placing small balls of solder on the pads of the die. The die is then placed upside down on the package substrate and the solder is re- flowed to make an electrical connection to the package bond pads. The pads are connected directly to the package interconnects, as shown in Figure 5.7. Flip-chip technology is also said to be self-aligning because when the solder is re-flowed, the surface tension of the solder balls will pull the die into alignment with the bond pads on the package.

The series inductance of a flip-chip connection is much lower than that of a wire bond. The typical inductance is on the order of 0.1 nH, which is an order of magnitude smaller than that of a typical bond wire. Furthermore, the effect of crosstalk in a flip-chip connection can be ignored. The bonding pads for a flip-chip connection can be placed over the entire die, not just on the periphery. This will help to minimize die size when a large number of I/O cells are required.

Mechanically and thermally, however, flip-chip technology is dismal. The thermal coefficient of expansion must be very close between the die and the package substrate. Otherwise, when the die heats up, it will expand at a different rate than the package, and the solder connections will be strained and can break. Furthermore, the physical tolerances must be very tight since the only degree of freedom when placing the chips is the small size of the pads. Cooling is also more difficult with flip-chip technology because the die is physically lifted off the package by the solder balls, which dramatically reduces the heat transfer and subsequently increases the cost of the thermal solution. Table 5.1 compares wire bonding and flip-chip technology.

Table 5.1: Comparison of Wire Bond and Flip-Chip Technology

Series Inductance (nH) Minimum Pitch (mils) Placement I/O Cooling Wire

bond 1–5 4–6 Periphery only Easy

Flip chip 0.1 2–3 Entire surface Difficult