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Consider the connector in Figure 5.2. The connector pins essentially form a network of coupled inductors. For the purposes of this exercise, we consider three drivers, one power pin, and one ground pin. The target will be net 2. The total induced voltage on pin 2 due to current changes in itself and pins 1 and 3 is

(5.6)

where İn represents dIn/dt. Assuming that the currents and the slew rates for each buffer are

the same, a single-line equivalent model can be created to simplify the analysis (see Section 3.6.2):

(5.7)

Equations (5.6) through (5.8) demonstrate how multibit switching through the connector pins can cause pattern-dependent signal integrity problems by inducing inductive noise onto the nets. However, what is often neglected is the effect of the power and ground connection pins. Consider the circuit shown in Figure 5.3. This is a typical configuration for a GTL + bus. When output switches low, the N device is turned on and the P device is turned off. A high transition occurs in the opposite manner. Let's

Figure 5.3: Current path in a connector when the driver switches low.

consider what the current does when the bus is pulled low by the N device. The current will be pulled out of Vtt and will travel through the transmission line, the signal pin, down through

the N device, through the ground plane, through the ground pin, and back into the Vtt source.

This is depicted by the current loop in Figure 5.3. Since a transient current will flow though the ground pin, it will induce inductive noise into the system of Lgndİ. Subsequently, the

inductance of the ground return path must be considered in the analysis. This effect is magnified significantly if the return current from several buffers shares the same ground pin, as depicted in Figure 5.4. In this particular case, the noise induced into the system would be 3Lgndİ, because three times as much current is flowing through the same ground pin. The

same phenomenon holds true when transient current is flowing through the power pin. Care must be taken to understand how the return currents flow for the particular bus so that the effect of transient currents through the power and ground pins can be accounted for properly during the connector design. Various return current path scenarios for GTL and CMOS bus designs and their impact on the signal are explored in much greater detail in Chapter 6. It is imperative that the return current paths be understood so that the connector design can be optimized.

Figure 5.4: Current path in a connector with several drivers.

For the time being, let's assume that the return current will flow entirely back through the ground pin as depicted in Figures 5.3 and 5.4. To derive the effect of an inductance in the

current return path, refer to Figure 5.5. Figure 5.5a represents a system of three inductive signal pins coupled to an inductive ground return pin. Note that all of the current flowing through the three signal inductors must return through the ground inductor. The effect of the ground return pin can be represented as shown in Figure 5.5b, assuming that the inductors are modified to include the inductive effects of the return path pin. This makes it easier to see the effect that an inductive pin in the ground return path has on the signal. The response of the system is shown in the following set of equations, which represent the response of Figure 5.5a:

(5.9)

is the voltage given by the simplified model. The result of (5.9) can easily be extended to a group of n conductors with a single current return path:

(5.10)

where the voltage in Figure 5.5b is given by (5.11)

Note that the effective inductance is simply the signal pin inductance, plus the ground return pin inductance, minus the mutual inductance.

Figure 5.5: Incorporating return inductance into the signal conductor: (a) three inductive

signal pins coupled to an inductive ground return pin; (b) effect of the ground return pin. It should also be noted that the equations above are valid only for a coupled array of pins. The total return path inductance will increase with distance from the corresponding signal pin and should be modeled separately assuming that the path is significantly long or the total return path inductance is much greater than Lgg. The total current return inductance is the

sum of the pin inductance and the inductance of the path to and from the return pin. The larger the total loop area in which the current flows, the larger the inductance. For example, the total loop inductance of loop A in Figure 5.4 has the largest total inductance, and loop C is the smallest.

Since the ground pins must return current to the power supply and the power pins must supply it to the drivers, low inductance is typically required for both power and ground paths to minimize inductive noise whether the return currents are flowing in the power or ground pins. Subsequently, it is generally optimal to maximize the total number of power and ground pins to decrease the total inductive path. In the equations above, it will effectively decrease

Lgg. Furthermore, it is usually optimal to place power and ground pins adjacent to each other

because the currents flows in opposite directions. Subsequently, the total inductance of the ground and power pins is reduced by the mutual inductance.

5.2.5. EMI

Another detrimental effect of a bad connector design is increased EMI radiation, covered in detail in Chapter 10. Notice the large current loops in Figure 5.4. As explained in detail in Chapter 10, the area of the loop is proportional to the emission radiated. Connectors will also exacerbate simultaneous switching noise by increasing the inductance in the ground return path and signal paths. Simultaneous switching noise and ground return path analysis are covered in detail in Chapter 6.