The main difference of the following TDC firmware to the first firmware is the usage of manually placed logic blocks, which is a time consuming task. To make the placement easier, the TDC design was modified to have as little as possible logic in the time critical parts. In addition, the counter frequency was doubled to 320 MHz, so a TDC time bin size of below 1 ns can be reached. First, a reference channel was designed and verified. After this it was possible to move the verified TDC channel to another position on the FPGA, and the resulting channel had largely the same performance as the first channel. Furthermore, it was possible to realize a reliable 16 channel 5 bit TDC with this design. A time bin size of 0.78 ns was reached, a satisfactory size for LHCb Outer Tracker needs.
In the following subsection the second design of an FPGA-based TDC, which also uses the fast counter method, is discussed. The main blocks are the TDC block with encoding, the histogram block, the PCI block and the different control and measurement blocks. Only the new TDC core is shown, all other blocks are identical to the ones of the first design that were already described in Subsection 5.3.3. In addition, the manual placement of the logic elements of the TDC channel is described.
TDC block
The time measurement is implemented with one counter running synchronous to the LHC 40 MHz clock and two additional phase-shifted clocks. All three clock frequencies are 320 MHz. For a hit the value of the counter and the status of the two additional clocks are latched and used to determine the point in time inside the 25 ns period. The top of Figure 5.15 shows in a functional diagram (wave form diagram) how the counter and the two phase-shifted clocks sub-divide the LHC clock cycle. The counter clock and the two additional clocks are phase-shifted by 90◦ to each other.
Each TDC bock is built with one 3 bit counter, running at 8 times the LHC clock (∼320 MHz). Figure 5.16 shows a block diagram of a single TDC chan- nel. A dead-time free measurement every 25 ns is reached by using two time measurement elements for each TDC channel. Both time measurement elements alternately measure the time to guarantee a proper encoding. The counter clock is generated from the LHC clock with an enhanced Stratix PLL. In addition, two
5.3. Time measurements with the Stratix FPGA 69
Figure 5.15: Functional diagram (top) and encoding scheme (bot- tom) for the manually placed TDC design of the Stratix FPGA- based TDC.
320 MHz clocks are generated. The three clocks are phase-shifted by 90◦ to each other and they are synchronized to the LHC clock. The 3 bit counters subdivide the 25 ns LHC period by a factor of 8. The values of the two additional 320 MHz clocks are used to subdivide each counter period by the factor of 4. Each point in time in the 25 ns period can be identified with a fixed bit pattern of the counter and the clocks.
The hit signal triggers the latching of the counter value and the latching of the actual value of the 2 additional 320 MHz clocks of the flip-flop block in the corresponding time measurement element. To avoid setup and hold time viola- tions during the counter latching, the hit signal is synchronized to the inverted counter clock. In addition to the measured time value the hit signals triggers the setting of a hit bit. Each time measurement element has a single hit register. The outputs of the hit register, the counter flip-flop values and the 320 MHz clock flip-flops are connected to the encoding block.
Encoding block
The drift time (∆T) is calculated from the time information in the flip-flops. The counter running with the 320 MHz clock is taken as coarse counter. The two flip-flops latching the status of the phase-shifted 320 MHz clocks represent 4
70 Chapter 5. FPGA-based time measurement
Figure 5.16: Schematic of the TDC block for the second design of the Stratix FPGA-based TDC.
possible values and for each value a fine timing value is defined which is added to the coarse count. The encoding scheme is shown in the bottom of Figure 5.15. The encoding is implemented as follows: The value of the counter is shifted two bits to the left (multiplication by 4) and taken as coarse time value. In addition, the value of the second clock flip-flop is shifted one bit to the left (multiplication by 2) and added to the 5 bit coarse time. Moreover, the two clock flip-flops are compared and the inverted output is added also to the 5 bit TDC time. At the end of the encoding a constant is subtracted from the time value to reach a time value of zero at the beginning of the LHC clock period. The resulting time information has 5 bits. The encoding block is reset after the readout and is ready for the next measurement. For each time measurement element, there exists a single encoding block.
The outputs of the TDC block are the 5 bit time information and the corre- sponding hit bit, both information exist for the two time measurement elements. These outputs are connected with following logic blocks.
Manually placed TDC reference channel
All the time critical logic blocks were placed manually, using the time information from Quartus II for the signal delays between the different logic elements. These times are not very precise but they show roughly how big the signal delays are on the real chip. This is the reason why it is necessary to validate these numbers with measurements.
During the manual placement, emphasis must be put on equal signal delays for the different logic elements. One of the most important signals is the hit
5.3. Time measurements with the Stratix FPGA 71
signal, which triggers the latching of the counter value flip-flops and the clock flip-flops. The placement was chosen to reach a jitter for the hit signal as small as possible at the flip-flop positions. In addition, the delay of the counter outputs to the flip-flops was chosen to be equal for all 3 bits in both time measurement elements. A difficulty is that it is not possible to place all logic elements in a single logic array block, due to input constraints.
After creating one reference channel, this channel was copied to other positions on the FPGA to create more TDC channels. It was achieved to place 16 TDC channels on the left upper corner of the Stratix FPGA. Figure 5.17 shows the chip planner which presents the location of the firmware on the FPGA chip. The chip planner view shows how many logic blocks inside a logic array block are used for the different LAB of the Stratix FPGA. Rectangles with a light blue color are empty, dark blue means that the logic array block is completely occupied. The green rectangles show the RAM blocks and the brown rectangles at the border of the chip are I/O cells. The 16 TDC channels were placed in 16 lines, the time uncritical logic was placed by the Quartus II fitter. 64 channels would also be possible, as there are enough logic blocks available.
Figure 5.18 shows the layout of the reference channel. The TDC channels had to be placed in rows because the input pins for the different TDC channels are placed in neighboring I/O pins. It is not possible to shrink the design more because the amount of reset and clock signals for each logic block array are limited. The difficulty of constructing a reference channel is to place the logic blocks such that the delays between them are equal and in addition to fulfill the filling constraints of each logic array block.