In the following first the functional simulation with ModelSim is shown. After- wards, the measurements of the real performance are presented.
ModelSim simulation of the one counter TDC design
A simulation of the second TDC design was done with ModelSim. The functional simulation shows a working TDC design. The simulation is shown in Figure 5.19. The latching of the counter value and the latching of the states of the two additional clocks can be seen. The encoding is not shown.
The second design was tested successfully with 16 TDC channels, and the re- sults will be shown in this subsection. The behavior of the 16 channels is uniform, all channels have a good linearity and the bin size distribution is equal within 100 ps. It is possible to use the same type of encoding block for all the different channels.
72 Chapter 5. FPGA-based time measurement
Figure 5.17: Chip planner view of the Stratix chip for the 16 channel 5 bit TDC. The time criticial logic elements of the 16 TDC channels are placed in the red frame and the time uncritical logic blocks, placed by the Quartus II fitter, are shown in the green frame. The TDC channels are placed in rows.
5.3. Time measurements with the Stratix FPGA 73
Figure 5.18: Reference channel layout. Two TDC channels are shown arranged in two FPGA rows. The visible part of the TDC channels does not include the encoding blocks, which are located for each TDC channel further to the right in the row. In the firmware used logic blocks are colored brown and not used ones are white. For TDC channel 2 the logic blocks are colored in green for TME 1 and red for TME 2. In addition, the I/O pin is colored blue. The distribution of the hit signal in TDC channel 2 is shown with red arrows including labels with the expected signal delays between the logic blocks. The hit signals enters the chip at position 1. and is distributed to two logic blocks at position 2. used to select the hit signal for the corresponding even or odd LHC clock cycle. From this location the signal is distributed further to the corresponding hit flip-flop at position 3., the two flip-flops latching the status of the two phase-shifted clocks clk 1 and clk 2 at position 4. and to position 5. where the hit signal is synchronized to the inverted counter clock. The synchronized hit signal triggers the flip-flops at position 6. to latch the status of the counter at position 7.
74 Chapter 5. FPGA-based time measurement
Figure 5.19: ModelSim simulation of the second TDC design. The simulations shows the time period of 3 LHC clock cycles respec- tively 75 ns. The 40 MHz clock and the 20 MHz clock are shown in yellow. The counter values and the additional two 320 MHz clocks are visible in green. The phase-shift between the 320 MHz clocks is 90◦. The hit signal in this simulation is represented by a 20 MHz clock (red). Whenever the hit signal rises the first time during an LHC clock cycle, the hit signal is synchronized to the inverted counter clock to avoid setup and hold time violations. This signal is used to trigger the latching of the counter value into the corre- sponding three flip-flops (orange). The delay between the hit signal and the change in the flip-flops of the counter is caused by the hit signal synchronization. The latching of the 320 MHz clocks are not synchronized and so not delayed to the hit signal.
5.3. Time measurements with the Stratix FPGA 75
ior. Figure 5.20 shows the results for channel 15 as example. The 20 MHz clock was fed through the NIM delay element as described in 5.3.5. For each data point the mean of 40,000,000 hits was calculated and this value is plotted against the delay of the NIM delay element. The measurements of the first time measurement element are shown in blue and the measurements of the second one are shown in red. The linearity is good with a INL of 0.06 bins (0.05 ns) for both TMEs. The result is much smaller as for the 4 counter TDC which was placed by the Quartus II fitter.
Figure 5.20: Delay scan channel 15 of the manually placed TDC design for the Stratix FPGA.
Bin size measurement: The bin size measurement for the TDC channel 15 is shown in Figure 5.21. As hit signal, a 1.13 MHz clock from a function generator was used as described in Section 5.3.5. The bin size is proportional to the hits in the corresponding bin. An alternating pattern is visible from the large and small bins. This pattern is caused by the real phase-shift of the two additional 320 MHz clocks at the flip-flop inputs which is not exactly 90◦. The DNL for the TDC channel 15 TME 1 is 0.19 bins (0.15 ns) and for TME 2 0.22 bins (0.17 ns). This is much smaller than the DNL of the first TDC design. The manually placed TDC channels have a better performance than the TDC channel placed by the Quartus II fitter. The maximum difference for the bin sizes of all 16 channels is 200 ps. Figure 5.22 shows the bin sizes of the 16 TDC channels. The DNL for the 32 TME variates between 0.17 bins (0.13 ns) and 0.35 bins (0.27 ns). The bin size variation for different TDC channels of all 16 TDC channels is only 100 ps.