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When routing clock or high-threat signals, it is common practice to via the trace to a routing plane (e.g., x- or horizontal axis) and then via this same trace to another plane (e.g., y- or vertical axis) from source to load. It is generally assumed that if each and every trace is routed adjacent to an RF return path, there will be tight coupling of common-mode RF currents along the entire trace route. In reality, this assumption is partially incorrect.

As a signal trace jumps from one layer to another, RF return current tries to mirror image the trace route. When a trace is routed internal to a PCB

between two planar structures, commonly identified as the power and ground planes, or two planes with the same potential, return current is shared between these two planes. Return current can jump between different potential planes only at a location where there are decoupling capacitors. If both planes are at the same potential (0V-reference), the RF return current jump will occur at a location where a via connects both 0V-references planes together, using the component's ground pin assigned to that via.

When a jump is made from a horizontal to a vertical layer, the RF return current cannot fully make this jump. This is because a discontinuity was placed in the trace route by a layer jump. The return current must now find an alternate, low-inductance (impedance) path to complete its route. This alternate path may not exist in a position that is immediately adjacent to the location of the layer jump, or via. Therefore, RF currents on the signal trace can couple to other circuits and pose problems as both crosstalk and EMI.

Use of vias in a trace route will always create a concern in any high-speed design.

To minimize development of EMI and crosstalk owing to layer jumping, the following design techniques have been found effective:

1. Route all clock and high-threat signal traces on only one routing layer as the initial approach concept. This means that both x- and y-axis routes are in the same plane. (Note: The PCB designer will likely reject this technique as unacceptable, because it makes autorouting of the board nearly impossible.)

consist of a silicon die and lead-bond wires encapsulated within a package. Common-mode energy developed internal to the component will most likely be the cause of EMI, not the trace itself. The same

radiated effect will be observed on periodic signal traces that are routed stripline, if proper layout techniques are not implemented. The majority of EMI problems observed in high-speed products is from component radiation, not trace radiation.

ƒ Stripline is optimal for suppression of RF currents developed within the signal trace. This suppression of radiated energy is the result of having image planes on both sides of the trace. Because magnetic flux is present within the transmission line, these fields become captured by the adjacent planes. Because of skin effect, the energy absorbed will be observed only on the internal skin of the metallic conductor. RF energy cannot travel through solid planar structures.

Routing signals stripline also cause a decrease in signal propagation between source and load. Slowing of the electromagnetic field is due to additional distributed capacitance present on both sides of the

transmission line. Unlike microstrip, with distributed capacitance on only one side of the trace, the additional capacitance on both sides may be enough to affect the propagation speed of the signal. Signal transition edges in the nanosecond and sub-nanosecond range may be skewed by this capacitive effect. In addition, stripline signals are surrounded 100% by a dielectric, which is another factor in slowing down the propagational speed.

2. Verify that a solid RF return path is adjacent to the routing layer, with no discontinuities in the route created by use of vias or jumping the trace to another routing plane.

If a via must be used for routing a sensitive trace, high-threat or clock signal between the horizontal and vertical routing layer, ground vias must be incorporated at "each and every" location where the signal axis jumps are executed. A ground via is always at 0V-potential. A ground via is a via placed directly adjacent to each signal route jump from the horizontal to a vertical routing layer. Ground vias can be used only when there is more than one 0V-reference plane internal to the PCB. This via is connected to all ground planes (0V-reference) that serve as the RF return path for signal return currents. This via ties all 0V-reference planes together adjacent, and parallel to, the signal trace jump location. When two ground vias are used per signal trace, a continuous RF path will be present for the return current throughout its entire trace route.^[3]

What happens when only one 0V-reference (ground) plane is provided and the alternate plane is at voltage potential, commonly found with four-layer stackups? To maintain a constant return path for RF currents, the 0V (ground) plane should be allowed to act as the primary return path. The majority of the signal trace must be routed against this 0V-plane. When the trace routes against the power plane, after jumping layers, use of a ground trace is required only on the layer adjacent to the power plane layer. This ground trace must connect to the ground plane, by vias, at both ends. This trace must also be parallel to the signal trace at a distance spacing that is as close as manufacturable. Using this configuration, we now maintain a constant RF return path throughout the entire route (Fig. 4.15).

Figure 4.15: Routing a ground trace to assure a complete RF return

path exists.

How can we minimize the use of ground vias when layer jumping is mandatory? In a properly designed PCB, the first traces to be routed are clock or high-threat signals, which must be "manually routed!" The PCB designer is permitted much freedom in routing the first few traces. The designer is then able to route the rest of the board using direct-line routing (shortest Manhattan length). These first few routed traces must make a layer jump adjacent to the ground pin via of a component. This layer jump will co-share this component's ground pin. This joint ground pin will provide both 0V-references to the component, while allowing RF return current to make the layer jump, as detailed in Fig. 4.16.

Figure 4.16: How to route the first trace within a PCB.

[3]Use of ground vias was first identified and presented to industry by W.

Michael King. Ground vias are also described in [1 and 10].

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Table of Contents 4.4: CAPACITIVE LOADING OF SIGNAL TRACES

Chapter 4 - Clock Circuits, Trace Routing, and Terminations

Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition by Mark I. Montrose

IEEE Press © 2000 Recommend this title?

4.10 CROSSTALK