The protection strategy is initiated with dc fault detection. It includes overcurrent, undervolt- age and current derivative methods, as given in Section 4.2. The first criterion to be met leads to fault detection in a dc relay. A dc fault is typically detected within 1 ms after the arrival of the first transient wave.
6.4.2
FB Converter Blocking
The blocking of a FB converter occurs due to three reasons. Firstly, it protects the submodule’s IGBTs from overcurrent events. Secondly, it stops the submodule capacitive discharge to the dc side fault. Lastly, it blocks the converter fault current. The FB converter blocking order is triggered by two criteria if:
1. In a converter station, an overcurrent is detected in the positive or negative pole. The overcurrent threshold is 2.4 kA while the nominal dc current is 2 kA. The blocking order has a delay of 0.1 ms.
2. In a dc relay, a dc fault is detected by overcurrent or undervoltage means. In this case, the blocking order arrives with a 2 ms delay due to processing requirements in the busbar station.
After receiving a blocking order, the firing pulses of converters stop. This leads to a suppression of arm currents within a few milliseconds. This time period (Tf all0in Eq. 6.4) is approximately 2 ms in the dc grid model of this thesis.
6.4.3
Discrimination of FDs
Immediately after dc fault detection, the discrimination algorithm starts. This algorithm analyses local data acquired at a dc relay. Then the algorithm classifies an FD, associated with the dc relay nearby, as internal or external to the faulty link.
Fault discrimination methods are detailed in Section 4.3. The FD classification algorithm is composed of two criteria. The first criterion comprises the sign of current derivative algorithm (given in Section 4.3.2). This methodology is able to discriminate at least half of the FDs at non-faulty links. The second criterion comprises the CCRC algorithm (given
6.4 Protection Strategy Description 107
in Section 4.3.1). This criterion aim to discriminate faults taking into account the sign and potential variations of the current change rate within a short time period. This period is typically less than 2 ms as it comprises the time between the dc fault detection until the converter blocking instant. Therefore at the converter blocking instant, the discrimination algorithm classifies an FD as internal or external to a faulty dc link.
6.4.4
Overvoltage Suppression
A voltage shift and overvoltage appears in the case of a P2Gnd fault in a symmetrical monopole dc network. The overvoltage must be quickly suppressed in order to prevent harmful conditions to dc equipment. Section 6.3 describes a method to suppress overvoltage and voltage imbalance in dc grids equipped with FB converters.
The method ensures a fast overvoltage decay rate, a low and symmetrical voltage level and no harmful converter arms currents. The duration of the process is typically 10 ms.
6.4.5
Fault Isolation
Fault isolation is ensured by the opening of the FDs placed at the faulty link ends. FDs have an operation delay of 10 ms and open once the dc current decays below the residual current breaking capability (assumed previously as 30 A).
The protection strategy has a minimum opening approach. This means that only the FDs in the faulty link should open. The opening of FDs following a dc fault is dictated by the discrimination algorithm. If an FD is discriminated as internal, the dc link is discriminated as faulty and the FD opens. If the dc link is classified as non-faulty, the FD remains closed.
6.4.6
Grid Restoration
After fault clearance and fault isolation, dc grid restoration is initiated by the de-blocking of FB converters. The converters operating as rectifiers at the pre-fault instants restore the dc voltage. Shortly after, the converters operating as inverters at the pre-fault instants restore the dc power flow. The de-blocking of a rectifier occurs if any of the following conditions are met:
1. Discriminated FD opening operation:
If the FDs discriminated as internal to the faulty link are open, the fault is isolated. Therefore, the converters are able to de-block and resume operation. The de-blocking order has a practical time delay of 5 ms. This period is considered due to likely opening delay between the discriminated FDs at both ends of the faulty link.
2. Voltage recovery:
The recovery of link dc voltage at a busbar indicates the grid restoration has started by converters connected to a remote busbar. Therefore, a converter shall be de-blocked if local dc voltage recovers approximately to nominal values. The voltage thresholds given in Section 4.3.3 are considered in this criterion.
3. Maximum time in blocking mode:
Converters are de-blocked after a maximum time in blocking mode if there are no locally discriminated FD. This maximum time is set as 200 ms which is sufficient to guarantee fault isolation (as it typically occurs in less than 150 ms).
The de-blocking of a converter in inverter mode occurs once the voltage recovery criterion is met. In this way, the power exchange between ac and dc grids keeps the same direction at both the pre-fault and the grid recovery periods. Succinctly, an ac grid exporting power at the pre-fault instant will export power during grid recovery by means of a converter in rectifier operation. Conversely, an ac grid importing power at the pre-fault instant will import power during grid recovery by means of a converter in inverter operation.
In a few cases, an FD might open in a non-faulty dc link. Therefore, grid restoration would be terminated by re-closure of such FDs. The re-closing criterion is based on the voltage recovery algorithm as given in Section 4.3.3.
At the end of the protection strategy, only the FDs placed on the faulty link are in the open state. The FB converters are de-blocked and their control operation is resumed.
6.5 Simulation Results 109
6.5
Simulation Results
The 4-terminal dc grid introduced in Section 3.2 is considered for fault simulations in this chapter. The grid includes 4 FB converters for fault current clearance and an FD at each link end for fault isolation.
Two fault scenarios are described in detail in this section, including a P2P and a P2Gnd fault. Fig. 6.6 illustrates the location of the dc faults in the dc network. A P2P fault occurs at 20 ms at link 12, 20 km from relay 12 and 180 km from relay 21, and has an impedance of 0.1 Ω. A P2Gnd fault occurs at 20 ms at the middle of link 24 (i.e. 75 km from relay 24 and relay 42) and has an resistance of 10 Ω.
B1 B4 B2 B3 12 21 23 32 24 42 Fast dc disconnector Link 12 Link 23 14 41 Li n k 14 FB Converter 1 P2Gnd fault P2P fault FB Converter 4 FB Converter 2 FB Converter 3
Fig. 6.6 MTDC grid case study with FB converters. The location of the fault scenarios is shown.
6.5.1
Pole-to-Pole Fault
A P2P fault causes a quick voltage collapse over all the network. Due to the significant disturbance caused, dc fault detection is achieved in a few time samples after the arrival of the transient waves at each dc relay .
Converters block following fault detection at a dc relay or at the converter station. Fig. 6.7 illustrates the converter blocking state. As observed, all the converters block shortly after the start of the dc fault.
Fault discrimination algorithms are initiated following fault detection in a dc relay. These algorithms analyse local dc current in order to classify their associated FD as internal or
0 20 40 60 80 100 120 140 160 180 200 220 240 C1bk C2bk C3bk C4bk T [ms]
Fig. 6.7 Converter blocking P2P .
external to the faulty link. The CRCC and sign of current derivative algorithms (Section 4.3.1 and 4.3.2) are performed at this stage. DC relays 12, 21, 32, and 41 experience a positive rate of change following the arrival of transient waves. These are potentially internal to the faulty dc link, according to the sign of the current derivative algorithm. At this stage, partial discrimination is achieved. To achieve full discrimination, only the two relays in the faulty link should be discriminated as internal. The CRCC criterion gives that level of discrimination whose performance is described for an internal and for an external relay.
Fig. 6.8 illustrates the behaviour of the CRCC algorithm on dc relay 21 which is internal to the faulty link. Shortly after 20.5 ms, the transient waves arrive at dc relay 21. Fault detection is quickly achieved as marked by ’Fdet2’ in Fig. 6.8 (c). At the same instant, the discrimination criterion of sign of current derivative classified this relay as potentially internal to the faulty link, ’Sdidt21’ in Fig. 6.8 (c).
The second current derivative is illustrated in Fig. 6.8 (b). It should be noticed that the negative values are omitted for visual clarity. In Fig. 6.8 (b), attention shall be paid to the maximum of the curve. In relay 21, there are two maxima identified, ’MaxInc21’ and
’MaxRef21’. The first maximum is associated with the incident transient wave while the
second is associated with the first reflected wave. By comparing these values, the magnitude of the first maximum is higher than the magnitude of the second, as marked by ’CRCC21’ in
Fig. 6.8 (c). The signal ’CRCC21’ remains true (thick line) during the fault discrimination
period which starts with fault detection and ends with converter blocking ’C2blk’. Therefore with converter blocking, the decision to open or keep closed the local FD is given. For the
6.5 Simulation Results 111 -0.5 0 0.5 1 1.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 Ip21 T [ms] DC Curre nt [p u] -10 0 10 20 30 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 d2I21dt2 MaxInc21 MaxRef21 d2Ip dt [p u/ ms2] T [ms] 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 Fdet2 C2blk Sdidt21 CRCC21 FD21or T [ms] (a) (b) (c)
Fig. 6.8 Data analysed by the discrimination algorithms in the internal dc relay 21. View of (a) dc current, (b) second derivative of dc current together with MaxInc and MaxRef of CRCC criterion and (c) protection signals.
internal relay 21, as ’CRCC21’ is true, an order to open the FD 21 is given (’FD21or’ in Fig.
6.8 (c)).
Fig. 6.9 illustrates the behaviour of the CRCC algorithm on dc relay 41 which is external to the faulty link. Shortly after 21 ms, the transient waves arrive at dc relay 41. Fault detection based on overcurrent or undervoltage is achieved after 22 ms (see ’Fdet4’ in Fig. 6.9 (c)). However, the start of the discrimination algorithm at this instant (of ≈ 22 ms) would mean that previously observed transient currents would not be considered for online analysis. Such a fault detection delay could lead to misjudgement of the CRCC criterion as the incident wave appears before the fault detection flag ’Fdet4’. In order to avoid this problem, the discrimination algorithm is initiated with fault detection (overcurrent or undervoltage algorithm) or disturbance detection (current derivative algorithm). In this way, fault discrimination is initiated at ≈ 21.5 ms.
In dc relay 41, a dc current disturbance is detected a few time samples after the arrival of the transient waves due to the sensitive current derivative method. This event initiates
0.4 0.9 1.4 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 Ip41 T [ms] DC Curre nt [p u] -1 0 1 2 3 4 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 d2I41dt2 MaxInc41 MaxRef41 d2Ip dt [pu /m s2] T [ms] 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 Fdet4 C4blk Sdidt41 CRCC41 FD41or T [ms] (a) (b) (c)
Fig. 6.9 Data analysed by the CRCC discrimination criterion in the external dc relay 41.
the discrimination algorithm. At the same instant, the discrimination criterion of the sign of current derivative classifies this relay as potentially internal to the faulty link (see signal ’Sdidt41’ in Fig. 6.9 (c)).
The second current derivative is illustrated in Fig. 6.9 (b). In relay 41, there are two maxima identified, ’MaxInc41’ and ’MaxRef41’. ’MaxInc41’ is associated with the incident
transient wave while ’MaxRef41’ is associated to the local maximum of the reflected waves.
By comparing these values at the converter blocking instant, the magnitude of the first maximum is smaller than the magnitude of the second. With converter blocking (’C4blk’ at ≈ 23 ms), the decision to open or keep the local FD closed is given. Therefore, at this instant the fault is classified as external to link 14 (where relay 41 is placed). As a consequence, the FD 41 order remains closed (with zero value as shown by ’FD41or’ in Fig. 6.9 (c)).
Fig. 6.10 illustrates the state of FDs during the application of the protection strategy. The thin line represents the closing mode while the thick line represents the opening mode. FDs placed at the faulty link include FD 12 and FD 21. With the proposed protection strategy, only the two FDs at the faulty link open.
6.5 Simulation Results 113 0 20 40 60 80 100 120 140 160 180 200 220 240 FD12 FD21 FD23 FD32 FD24 FD42 FD14 FD41 T [ms]
Fig. 6.10 State of FDs following the dc P2P fault.
Fig. 6.11 illustrates dc currents and voltages at the dc grid. The converter dc current is quickly interrupted with blocking actions. As shown previously in Fig. 6.7, converter C2 is the first to de-block. This converter restores smoothly the dc link voltage while current is kept within nominal values. The currents and voltages are not shown as they are identically symmetric to the positive pole values.
6.5.2
Pole-to-Ground Fault
A positive-P2Gnd fault occurs at 20 ms in link 24. This event causes a voltage shift in the monopole networks. Therefore, an overvoltage appears at the non-faulty pole which is suppressed with the methodology presented in Section 6.3.
Fault detection occurs quickly after the arrival of the transient waves. This event leads to blocking of FB converters as illustrated in Fig. 6.12.
The next step of the protection strategy comprises fault discrimination. Considering the discriminative algorithm based upon the sign of current derivative, each busbar unit classifies one FD as potentially internal to the faulty link. The potentially internal FDs are associated with an increasing behaviour of the current derivative at the fault detection instant. In this fault case, FDs 12, 24, 32 and 42 are discriminated as potentially internal to the faulty link. In order to reduce the number of discriminated FDs, the CRCC discrimination criterion is considered.
-0.5 -0.25 0 0.25 0.5 0.75 0 20 40 60 80 100 120 140 160 180 200 220 240 V12p V23p V24p V14Ap T [ms] DC Vo ltage [p u] -2 -1 0 1 2 3 4 0 20 40 60 80 100 120 140 160 180 200 220 240 C1Ip C2Ip C3Ip C4Ip DC Curre nt [k A] T [ms] (a) (b)
Fig. 6.11 DC currents and voltages at the network.
0 20 40 60 80 100 120 140 160 180 200 220 240 C1bk C2bk C3bk C4bk T [ms]
Fig. 6.12 Converter blocking with P2Gnd.
Fig. 6.13 illustrates protection related data of dc relay 24 which is internal to the faulty link. The dc current at relay 24 in Fig. 6.13 (a) has an increasing behaviour at fault detection (≈ 20.5 ms) which meets the sign of current derivative criterion. This results in the flag of the signal ’Sdidt24’ as shown in Fig. 6.13 (c).
6.5 Simulation Results 115
Fig. 6.13 (b) shows the second order current derivative at relay 24, together with forward transient waves. At the start of the fault, a large rate of change of dc current is noticed due to the capacitive discharge of the faulty link which is a dc cable in this case. Afterwards, the dc fault current keeps increasing until converter blocking (’C2blk’ in Fig. 6.13 (b)), but the rate of change diminishes. During the discrimination period, between fault detection and converter blocking, only one forward transient wave is detected which is related to the incident transient wave. The second maximum (’MaxRef24’), is numerically coded to be
identified immediately after the achievement of ’MaxInc24’. For this reason, ’MaxRef24’ in
Fig. 6.13 (b) does not correspond to the maximum local of reflected waves. Nonetheless, the decision making is not altered due to this performance.
-0.5 0 0.5 1 1.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 Ip24 T [ms] DC Curre nt [p u] -5 0 5 10 15 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 d2I24dt2 MaxInc24 MaxRef24 d2Ip dt [p u/ ms2] T [ms] 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 Fdet2 C2blk Sdidt24 CRCC24 FD24or T [ms] (a) (b) (c)
Fig. 6.13 Data analysed by the CRCC discrimination criterion in the internal dc relay 24.
By comparing the magnitudes ’MaxInc24’ and ’MaxRef24’ (in Fig. 6.13 (b)), the maxi-
mum of the incident wave is larger. This leads to discrimination of FD 24 as internal to the faulty link. Correspondingly, the discrimination signal ’CRCC24’ remains with value one
(thick line). An opening order to the FD 24 is given. However, this order only occurs after overvoltage suppression actions. For this reason, ’FD24or’ in Fig. 6.13 (c) remains with a zero value in the visualised period.
Fig. 6.14 illustrates protection related data of dc relay 32, which is external to the faulty link. The dc current at relay 32 (see Fig. 6.14 (a)) has an increasing behaviour at fault detection (after 21 ms), which meets the sign of current derivative criterion. This results in the flag of signal ’Sdidt32’ (see Fig. 6.14 (c)).
Fig. 6.14 (b) shows the second order current derivative at relay 32, together with forward transient waves. In this figure, forward incident and reflected waves can be observable. The magnitude of these waves is associated with the signals ’MaxInc32’ and ’MaxRef32’, used in
the CRCC discrimination algorithm . It should be noticed that the reflected wave starts at ≈ 22.3 ms (see Fig. 6.14 (b)). This event occurs at ≈ 0.55 ms after the blocking of converter C2 which occurs at ≈ 21.8 ms (’C2blk’ in Fig. 6.13 (c)). The ≈ 0.55 ms interval corresponds to the propagation delay of cable 23 which has a length of 100 km . Therefore, the blocking of converters downstream external dc relays (i.e. converters placed between an external dc relay and the fault location) cause transient waves that propagate together with reflected transient waves. This reason supports the higher magnitude of reflected waves in comparison to the incident wave at external dc relays. By comparing the magnitudes of ’MaxInc32’ and
’MaxRef32’ at the decision making instant, i.e. at converter C3 blocking (≈ 23.4 ms in Fig.
6.14 (c)), the reflected wave ’MaxRef32’ achieved a larger value than the incident wave
’MaxInc32’. As a result, dc relay 32 is discriminated as external to the fault link. Therefore,
FD 32 remains closed during the application of the protection strategy.
Fig. 6.15 illustrates the dc voltage on the positive and on the negative poles following the P2Gnd fault in link 24. The voltage is measured at busbar 2. Fig. 6.15 (a) shows the voltage with natural overvoltage decay at the non-faulty (negative) pole. Fig. 6.15 (b) shows the dc voltage with the application of the overvoltage suppression method, described in Section 6.3. As observed, the method based on the bypass of FB converter arms leads to a quick overvoltage suppression at the network.
Once a residual dc voltage is achieved at both poles, the discriminated FDs receive an opening order. In this fault case, these are the FDs 24 and 42. Fig. 6.16 illustrates the state of the FDs in the dc network. As observed, only the FDs placed at the faulty link open.
Fig. 6.17 illustrates dc current and positive and negative pole dc voltages. The dc current increases immediately after the start of the fault. Concurrently, the dc voltage experiences a shift where the non-faulty negative pole enters an overvoltage area. This overvoltage is