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All along the course digital circuits have been designed with components such as logic gates, multiplexers, and flip-flops. The result of the design work is a logic diagram of the type shown in Fig.7.1.

How can such a logic diagram be physically implemented? A first option is to use standard (off the shelf) small-scale, medium-scale, and large-scale integrated circuits, capacitors, resistors, and other passive components, and to interconnect them on a printed circuit board (PCB). An example of digital system implemented in this way is shown in Fig.7.2.

Another option is to design and manufacture a new specific integrated circuit.

Consider the first option. Two examples of standard small-scale integrated circuits (chips) are shown in Fig. 7.3. The first (Fig. 7.3a) is a chip that integrates four AND2 gates and the second (Fig.7.3b) is a chip that integrates three NOR3 gates. Figure7.3shows the internal logic circuit, a photograph of the package, and the assignment of package pins to internal logic signals. For every chip, the vendor gives to the designer a data sheet that defines the logic and electrical characteristics of the component, the mechanical characteristics of the package, the pin assignment, and so on.

It remains to interconnect the components (standard chips, discrete electrical components, mechanical switches). During the development phase of a new digital system, a prototyping board like that of Fig. 7.4a can be used: the components are plugged into the board holes and the connections are made with wires (Fig. 7.4b). Obviously circuits implemented with this type of connections (plugged-in wires) are not very reliable but are quite similar to the final system and permit to test their interaction with other systems.

Once the prototype has been satisfactorily tested, a PCB is designed and manufactured. It includes the holes within which the chip pins will be inserted (through-hole technology) and the metal tracks that implement the connections. Nowadays surface-mount devices (SMD) are also used; those components can be placed directly onto the surface of thePCB(surface-mount technology). A system similar to that of Fig.7.2is obtained. Current EDA tools permit to design the PCB and to simulate the complete system before the manufacturing of the PCB.

# Springer International Publishing Switzerland 2017

J.-P. Deschamps et al.,Digital Systems, DOI 10.1007/978-3-319-41198-9_7

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The use of standard components is a convenient option in the case of small circuits. In the case of large circuits, a better option could be the development of a new, large-scale, integrated circuit, a so-called application-specific integrated circuit (ASIC) that integrates most functions of the system under development.

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Fig. 7.1 Example of logic diagram

Fig. 7.2 Example of physical implementation

An integrated circuit (IC) package is shown in Fig. 7.5a. Within the package, there is a small silicon die that integrates the whole circuit. It is connected by very thin wires to small metal tracks.

Those tracks are connected to the external pins of the package.

The technology used to manufacture integrated circuits is microelectronics. It permits to integrate electronic circuits on a semiconductor substrate, most often silicon. The fabrication consists of several processes such as oxidation of the silicon slice, deposition of some layer, etching of the deposited layer, iron implementations, and others. Most of those processes need a mask because at each step certain areas must be masked out. As an example,p-type transistors are integrated within n-type wells that are created by implanting negative ions within the corresponding area. So, a masking technique is used to implant negative ions only within thep-type transistor areas.

Fig. 7.3 Two examples of small-scale integrated circuits

Fig. 7.4 Prototyping board

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The integration density in terms of transistors per square millimeter is very high. As an example, the Intel Core i7 includes more than 700 million transistors within less than 300 mm².

The information that an IC production line (a silicon foundry) needs to manufacture a circuit is the layout (Fig.7.6): it is the geometric information necessary to fabricate the masks. As mentioned above, most fabrication steps need a specific mask. For example, a first mask defines the areas where there are transistors (active areas); another mask defines the areas where there arep-type transistors, and so on. Then, using the layout information, a set of masks is fabricated (Fig.7.6). They are used to process silicon slices (silicon wafers) with a diameter of up to 300 mm. In Fig.7.6each square on the wafer surface is a circuit, so that a lot of ICs are manufactured at the same time. Once the wafer has been processed, it must be cut—it’s the dicing process—and each die must be encapsulated in a package.

The generation of the layout, from a logic diagram, is not an easy task. As an example, Fig.7.7b shows the layout of a CMOS inverter whose electrical circuit is shown in Fig.7.7a, and a cross section Fig. 7.5 Integrated circuit

Masks (one per layer) Silicon wafer

Mask generation

Technological processing

Dicing

Dies

Chip

Active area mask

P diffusion mask ...etc Layout

Fig. 7.6 IC manufacturing

AA⁰ of the device to be manufactured is shown in Fig. 7.7c. The circuit consists of only two transistors, ann-type transistor and a p-type transistor. Each color defines a different mask. For example, the blue areas correspond to a mask used to define the metal tracks. The red areas correspond to polysilicon layers that are the transistor gates; observe that the n-type and p-type transistor gates are defined by a common polysilicon (red) area that is also the gate input. The green areas correspond ton-type or p-type diffusion layers that are the sources and drains of the transistors.

The yellow areas correspond ton-type wells within which p-type transistors will be integrated, and so on. A detailed description of the manufacturing process can be found in many books on microelec-tronics, IC design, manufacturing, etc., for example Chapter 2 of Rabaey et al. (2003).

The conclusion is that the design of a circuit integrating hundreds of thousands of logic gates implies the generation of millions of geometric forms (rectangles, squares), with several colors representing the layer types (metal, polysilicon, diffusion, wells, contact holes between layers, etc.). Furthermore

• There is a set of design rules that must be taken into account, for example the minimum width of a polysilicon layer, the minimum distance between two metal tracks, and many others.

• The size of (at least part of) the geometric forms must be computed; as an example, the delay of a gate directly depends on the size of the corresponding transistors.

How to manage such a complex task? The answer is

• The use of implementation strategies such as standard cell approach, gate array approach, and field programmable gate arrays (FPGA)

• The development and use of electronic design automation (EDA) tools Fig. 7.7 CMOS inverter layout

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