El utilitarismo

Three implementation strategies are described: standard cell approach, mask programmable gate arrays, and FPGA.

7.2.1 Standard Cell Approach

This design method is based on the use of predefined libraries of cells. Those cells are logic components such as gates, flip flops, multiplexers, and registers. The layout of each cell is generated in advance and is stored in a cell library. To make the assembling of the circuit easy, all cells have the same height.

As an example, the layout of a NAND3 gate is shown in Fig.7.8. It integrates threen-type serially connected transistors in the lower part, and threep-type transistors connected in parallel in the upper part.

The layout of the circuit is generated by a place and route EDA tool. The cells are placed in rows whose height is the common cell height (Fig.7.9). Macrocells such as memories, multipliers, and Fig. 7.8 NAND3 cell

Functional module (RAM, multiplier,…)

Routing channel Logic cell

Feedthrough cell

Rows of cells

Height Fig. 7.9 Floor plan

processor cores can also be added. An example of resulting floor plan is shown in Fig.7.9. It consists of a set of rows of standard cells (previously designed and characterized cells). The space between rows is used to lay out connections. Sometimes feed-through cells (connections) are inserted. In many cases there are also macrocells.

As a matter of fact, in modern standard cell technologies there are no routing channels. The upper metal layers are used to lay out connections on top of the cells.

7.2.2 Mask Programmable Gate Arrays

The gate array approach consists in manufacturing in advance arrays of cells, without regard to the final application, but in such a way that only connections must be added to meet the circuit specification.

The floor plan is similar to that of a standard cell circuit. An example is shown in Fig. 7.10.

The floor plan consists of rows of uncommitted cells separated by routing channels. An uncommitted cell is an uncomplete logic component: to get an actual logic component, internal connections must be added. The floor plan of a particular gate array is predefined (cannot be modified). The number of rows, the size of the rows, and the distance between rows are predefined, and so is also the maximum number of cells and the maximum capacity in terms of logic gates. On the other hand, the gate array vendors offer families of components with different gate capacities and different maximum numbers of input and output pins.

An example of uncommitted cell is shown in Fig. 7.11a(layout) and7.11b(electrical circuit).

It contains fourp-type transistors and four n-type transistors. The red tracks are the common gates of the four transistor pairs.

Then (Fig. 7.12) by adding metal connections, a 4-input NOR gate is obtained. The fourp-type transistors are connected in series and the fourn-type transistors are connected in parallel between Out and GND.

As in the case of standard cells, in modern gate arrays there are no more routing channels. The connections are laid out on top of the cells. Those channelless gate arrays are sometimes called seas of gates.

7.2.3 Field Programmable Gate Arrays

An FPGA is similar to a gate array but it is user programmable. An example of floor plan is shown in Fig.7.13. The device consists of a set of programmable basic cells and of programmable connections.

Row of

uncommitted cells

Routing channel Fig. 7.10 Gate array

floor plan

7.2 Implementation Strategies 185

a b

VDD

GND

VDD

GND

In1 In2 In3 In4 In1 In2 In3 In4

Out

Out

Fig. 7.12 NOR4 gate

Programmable basic cell

Programmable input / output

Programmable connection Fig. 7.13 FPGA floor plan

a. b.

VDD

GND

GND metal

polysilicon VDD

Fig. 7.11 Uncommitted cell

An example of simplified programmable basic cell is shown in Fig.7.14. It includes a look-up table (LUT), able to implement any 4-variable switching function, and a flip-flop. In function of the value of the configuration bit that controls a MUX2-1, the cell output is equal to the look-up table output or to the flip-flop output.

The connections between cells are also programmable. Three examples of connections between a vertical line and a horizontal line are shown in Fig.7.15. The first example (Fig.7.15a) is a transistor controlled by a configuration bit. The second example (Fig.7.15b) is an anti-fuse: it is a switch, initially open, that can be short-circuited by applying a (relatively) high voltage between its terminals.

The third example (Fig. 7.15c) is a floating-gate transistor: according to the amount of electric charges stored on the floating gate, this transistor conducts or doesn’t.

So, apart from the basic cell and from the connections, an FPGA also includes a lot of memory elements that store the configuration data, like an underlying static RAM, EEPROM, or OTP ROM (Sect.4.6.3).

FPGA devices also include macrocells. An example of medium-size commercial FPGA is shown in Fig.7.16. It includes logic cells (CLB), interface cells (IOB), RAM, and multipliers.

4-input

LUT D Q

reset 0 1 configuration bit

Input_3··0 Fig. 7.14 Programmable

basic cell

a. b. c.

configuration bit

antifuse floating gate

V_DO

Fig. 7.15 Programmable connections

Ram blocks Input / Output Block

(IOB)

Programmable interconnections

Multipliers

Configurable Logic Block (CLB)

Fig. 7.16 Commercial FPGA (courtesy of Xilinx)

7.2 Implementation Strategies 187

Modern FPGA are very large circuits. They permit to implement complete systems on a chip, including microprocessors and memory blocks. They constitute a very good option to fabricate prototypes. They can also be efficiently used in the case of low-quantity production.