Elementos de las hojas de trabajo

The FPGA board serves as the central control module and readout controller. The centerpiece of the general purpose board is a Xilinx Spartan-6 FPGA with multi-gigabit transceivers. An exter- nal USB 2.0 controller IC (FTDI FT2232H) connected through an 8-bit bidirectional FIFO bus establishes the connection to the control PC, allowing the transmission of both JTAG signals for FPGA programming as well as user data after programming through one common USB port. A programmable PLL IC (Analog Devices ADF4351) generates the low-jitter 695 MHz clock needed by the ASIC’s ADCs. Through a series of clock multiplexers and dividers, the clock is fed to the DUT as well as the FPGA, allowing synchronous operation of both devices.

The ASIC’s supply voltages are fed to the mainboard from connectors, offering the possibility to use a regulator board as in the final detector system or by plugging simpler replacement boards. The replacement boards used for the F1 ASIC tests feature three LT1764A regulators, each providing a peak current up to 3 A and an output voltage adjustable by the selection of a resistive divider. Digital control through five 3.3 V lines from the FPGA is available.

5.1 Hardware

Figure 5.2: FPGA board with Regulator Replacement Board attached. The core element, a Spartan-6 FPGA, creates precise timing signals for the readout ASIC under test, generates slow- control programming signals and forwards the data from the readout ASIC to the control PC via USB. Not visible, on the bottom: A 200 pin connector to the mainboard.

In the same way, connectors are provided to plug an I/O board, allowing to feed an ASIC’s data stream into the final readout hardware. An MGT link between the I/O board and the readout system FPGA board can be established as well, which allowed to test the I/O Board’s MGT capabilities before the PPT was available.

A large number of power and signal lines with various I/O standards are going to the mainboard, making the FPGA board a flexible tool for the readout system. For instance, 77 single-ended and 20 differential lines including dedicated clock lines are routed from the FPGA to the connector. These are used, for example, for distributing the differential XCLK and XDATA signals for fast control of the ASIC, and for the JTAG slow-control signals.

The FPGA board was initially developed at the chair in 2010. Modifications by the author were necessary during the course of the thesis, fixing power supply problems and expanding the connec- tion possibilities to external devices through additional connectors. External devices can since be run synchronously to the device under test, or the system can be triggered by other devices, e.g. in a test beam environment. The board is also very compact with a size of 110 x 117.5 mm2.

The latest design change by the author included a complete rework of the board, mainly to in- corporate a USB 3.0 connection to the host PC in order to overcome a bandwidth bottleneck. More details about the data bandwidth can be found in section 5.2.

5.1.2 Mainboard

The mainboard serves as the central board for interconnection to the ASIC and sensor bias distri- bution PCB in the setup. Several iterations of this board were necessary to support changes in ASIC

Figure 5.3: Last generation of the DSSC test system mainboard. Left: Connector to the FPGA Board. Bottom left: Connectors to ASIC/Sensor under test with hole for sensor irradiation. Right: Connectors for sensor ceramics and sensor biasing cable.

development or to meet the demands for improved measurements. The latest version of the board is shown in figure 5.3 with a size of 110 x 180 mm2.

On the left side, a large connector (200 pins) for the FPGA board can be found, delivering clock, control, and power signals. The ASIC carrier can be plugged next to it. Two connectors are used for the ASIC carrier to provide mechanical support, and to separate the sensitive analog supply and bias nodes from the digital lines. The large hole between the ASIC connectors allows for an unobstructed irradiation from the bottom, if needed.

A clock buffer and distributor IC (LMK01000) buffers the fast ADC clock and distributes two copies to the ASIC connector, allowing to use up to two ASICs in parallel. The IC features very low jitter (30 fs) and allows to delay the output clocks with respect to the input. The clock delay is used in the testsystem to shift the ASIC’s output data with respect to the sampling clock in the FPGA, that is generated from the non-delayed version of the clock.

A separate connector for stand-alone DEPFET sensors mounted to dedicated ceramics is visible on the right. All sensor bias voltages are routed to both the ASIC connector and the stand-alone sensor connector, with several lines between the two for the connection of sensor pixels to readout pixels.

While the ASIC supply voltages are delivered through the FPGA board connector, the bias volt- ages needed for sensor operation can be fed in flexibly via single cables as well as, more compact, by a 64 pin Samtec EEDP cable. The EEDP cable solution in principle also offers the possibility for digitally controlled bias voltages, as digital control lines are routed from the FPGA board to the connector. Supply and bias voltage decoupling has been implemented on the mainboard, offering the possibility to check different decoupling and ground connection schemes.

Circuits to generate the Clear, Clear gate and Inner Substrate pulses needed for DEPFET opera- tion and sensor-internal charge injection have been implemented using analog high-voltage multi- plexers. The circuitry is controlled by the FPGA and runs synchronously to the readout ASIC.

5.1 Hardware

The board also holds a temperature measurement circuit, consisting of an IC with a single pin PWM output whose duty cycle depends on the temperature. The output is digitized by the FPGA and is available for monitoring or temperature regulation in the user software. The sensor IC is placed close to the ASIC connectors in order to measure the temperature as close to the ASIC as (easily) possible.

5.1.3 Chip carriers

Being the most delicate part of the setup, the chip carrier boards hold the device under test and are essentially fanout boards. Control and readout signals are usually routed on the external layers, while the power to the ASIC and sensor assemblies are put on split power and ground planes in the inner layers to provide low impedance paths. When using bump-bonded sensor-ASIC assem- blies, a hole in the PCB is provided for wirebonding the high voltage needed for depletion from the backside. Through the hole, the sensor to be tested can be irradiated.

Figure 5.4: Left: Top view on a 64 x 64 MSDD and F1 assembly with the reflective entrance window visible. Right: Bottom view on the dense wirebonding area between carrier PCB and assembly, and the connectors.

The most complex carrier designed during the course of this thesis is a PCB designed to carry the large test structures containing a sensor and one or two bump-bonded F1 ASIC, depicted in figure 5.4. This can be a MSDD assembly, where only 64x64 pixel versions for one readout ASIC are available, or a DEPFET assembly, where a 128x64 version has been designed for two readout ASICs. In the latter case, in total 184 wirebonds on two opposite sides of the assembly are needed on a 150 µm pitch for the connection of the assembly. The 6-layer PCB delivers the power to the assembly on dedicated power and ground layers. All differential pairs, including the most sensitive ADC clock pair due to its influence on the bin size matching, is routed closely together with length matching, shielded from switching lines like the DEPFET clear.