Etapas para la formulación de un proyecto empresarial

This section presents the stability analysis for the N-Input current (reset) programming loop described in section 6.2.3.1, the schematic is shown in figure A.6. For a closed loop system, it is essential to make sure that the circuit is stable in the desired operating point. Furthermore it must be made sure that this operating point can be reached safely when powering the circuit. Simulation shows, that a DC operating point can be found for any bias current supplied by Rbias. For the operating point to be stable, negative DC feedback must be applied in the loop and the loop gain must have dropped to below unity before the phase of the loop has decreased by an additional 180◦_{. This is intuitive because} negative feedback plus a negative phase shift of 180◦ _{degrees essentially generates positive feedback} at the input if the gain is larger than unity. Positive feedback creates a pile-up effect at the input causing oscillations. The so-called phase margin is defined as the difference of phase at the unity gain crossover frequency and 180◦_{. The system is stable if the phase margin is positive, but it is susceptible} to ringing, the closer the phase margin gets to zero. For a large phase margin the system settles very slowly. A phase margin of 60◦ _{is generally considered the optimum value [28], delivering negligible} peaking while providing fast settling.

The filter input node contributes the most dominant pole of the system which is given by:

ω0= 1

Rout,ICON(1 + A)Cf

(A.310) where A is the open loop gain of the filter amplifier, R is the total resistance at the negative input of the amplifier and Cf is the integrator (filter) feedback capacitance. R is given by the output resistance of the ICON cell. The secondary pole is given by:

ω1=

1

ron,SwResCin+ cgd ,NgmNrds,N

TCascP ICON Integrator (FCF) VRes Storage SOURCE VSSS VSSA TGain TStab VDDA Pre- amplifier Cstray Cres Vref Bias Voltages SwProg SwProg SwProg SwRes QIn Vstore Vres TCascN ires ibias RICON

Figure A.6: Detailed view of the current programming loop. All SProg and the SRes switches are closed to establish the loop while SRes is pulsed to clear a collected signal from the input node.

where Cin is the total shunt capacitance at the input node ground and the and small signal parameters subscripted by N belong to the input NMOS transistor (TGain). Note that node vx (see figure A.5) is not a virtual ground node in the programming phase. The lowest resistance at vx (even without RICON is given by the channel resistance of TGain (rds,N). This situation configures the input branch as a voltage gain stage with a gain of AN = gmNrds,N. The gate-drain capacitance of TGain is therefore amplified by AN (Miller effect) making it non-negligible. To improve the stability, the most effective measure is to split the poles further apart in frequency. This can be achieved by

(1) Reducing ω0 with respect to ω1. This measure starts to dampen the gain at an earlier frequency, such that the gain crossover decreases in frequency increasing the phase margin.

(2) Increasing ω1 with respect to ω0. This measure is only effective if ω1 is pushed out far enough that its phase shift occurs when the loop gain is already sufficiently low.

Due to the enourmous DC loop gain of ≈ 109 dB the most effective means to generate additional pahse margin is to increase Cf and / or Rout,ICON. In Figure A.8, the phase margin is plotted against the Cf for different process corners. The maximum possible capacitance (due to area constraints) is 13 pF, for the (very extreme) fast-fast-functional corner (’fff’) a further increase of Rout,ICON is necessary to reach a phase margin of 60◦_.

−80 −60 −40 −20 0 20 40 60 80 10m 1 100 10k 1M 100M Lo op Gain (dB) Frequency (Hz) Cf=1 pF Cf=10 pF −400 −300 −200 −100 0 10m 1 100 10k 1M 100M Lo op Phase ( ◦) Frequency (Hz) Cf=1 pF Cf=10 pF

Figure A.7: Loop gain and phase of the closed programming loop. The phase margin can be incrased by increasing the amplifier feedback capacitance.

0 10 20 30 40 50 60 70 80 0 2 4 6 8 10 12 14 Phase Ma rgin ( ◦) Filter Cf (pF)

NInput IProg Stability vs. Corners

fff, icon 1/3 fff, icon 1/6 tt

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Acknowledgements

First of all I want thank my wife Denise for sharing her life with mine and especially for being so considerate and supportive during submission times. In between the numerous chip submissions for the DSSC project, two babies were born who are all the world to us. I thank my children for being who they are, making me laugh and bringing joy to my life. I thank my parents for raising me to the person I am and helping me to develop a researching character.

I thank my supervisor, Prof. Dr. Peter Fischer, for giving me the opportunity to work on this exciting project and giving me the chance to be creative and let ideas develop. He has always been appreciative of my work and it is a pleasure to work in his group. I want to further thank Prof. Dr. Ivan Peric, KIT, for his support and advices. I am especially grateful that I had the opportunity to present my work at a number of international conferences. All the people at the Chair for Circuit Design and Simulation I want to thank for the friendly and productive working environment.

Working in the DSSC collaboration has been a great pleasure both from the scientific and human perspective. The exchange and discussions especially with the collaborating groups from DESY, led by Dr. Karsten Hansen and from Politecnico di Milano, led by Prof. Dr. Carlo Fiorini have always been fruitful.

I also thank all proof readers and of course the referees for reporting on my thesis. I know I am scratching only the surface here on the people I need to thank, it is out of scope to thank everyone here explicitly. I sincerely hope that nobody feels forgotten.