3. Eighteen P2P connections between slots and fixed area used for bus requests.
The total amount of connection wires is 50 and are distributed in four FPGA rows. The TBUFs based interconnections use all the four rows, while all the 34 CLB connections use a single row. This has been possible by interleaving long CLB interconnection (see Figure 2.21). Differently, if the same amount of interconnections were implemented only with the TBUFs, 13 rows would be needed. Access points to the communication structure are designed using slightly modified long P2P vertical CLBs interconnections.
Every CLB used as an access point yields up to 8 signals (one per LUT). Connections between the access point and the communication structure are done by vertical CLB routing signals. In the case of TBUF based wires, access point signals are directly connected to TBUF inputs, while for connecting to CLB signal, a CLB LUT is used as a driver (see Figure 2.21). Again, for monitoring the behavior of the wires during partial reconfiguration, some of them have been connected to the IOBs in the bottom part of the FPGA.
Differently from the Bus-v1, access points in Bus-v2 are allocated six CLB rows from the slot border (see Figure 2.21. With this technique, better results in terms of signal routing within the slot boundaries have been achieved. A lot of wires have to be routed to access points, and the Place and Route (PAR) programs use HEX wires that span exactly six CLBs. Therefore with this solution, fewer wires cross the slot borders after the PAR process. Also, the amount of used CLBs have been reduced by eliminating the pass through CLBs (pass through CLBs can be seen in Figure 2.20). Instead of the pass through CLBs, wires have been concatenated simply using CLB switch matrices (see Figure 2.21.
All the files needed for the virtual architecture definition: the system and hard core templates, the macro structure files and the user constraint files have been created.
For testing purposes, on top of the communication structure, a simple synchronous bus protocol that uses 38 of the 50 available wires has been defined. Similarly to the previous reconfigurable system, here also a set of basic partial coarse grain reconfiguration of CLB columns have been performed to validate the system relocation feature.
Finally, it is important to remark that this reconfigurable system has been used as a base for creating a remotely reconfigurable device that will be presented in detail in Chapter 5.
2.5 Results
In Table 2.11, a feature summary of the one dimensional bus based architectures included in the state of the art section 2.1 and the architectures that could be design with the method proposed in this Chapter can be found. The proposed solution also covers 2D architectures, but they are the main topic of Chapter 3 that includes a similar features summary Table. It is important to clarify that in the Table, BM-Xilinx are refereed when the author has not specified the used macro type (CLB or TBUF), but it is clearly based on neighboring communication (Xilinx approach). Differently if data is available, the macro type has been specified (TBUFs or LUT). From all the performed tests and the features summary of the reconfigurable system presented in this Chapter, included
60 2.5 Results
Table 2.11:bus based 1D reconfigurable systems - features summary. Overall comparison of all the approaches presented in the state of the art section of the Chapter and other, based on the proposed in this thesis method.
Group Device Macros Comm.Type Relocation Slot grouping
Xilinx All BM-TBUFs/LUTs P2P No No
Lockwood FPX Virtex No Macros P2P restricted No
Horta et al. Virtex BM-TBUFs Bus No No
Moraes et al. Virtex II BM-LUTs Bus No No
Platzner et al. XF Virtex II BM-Xilinx BuS No No
Nollet et al. Virtex II BM-Xilinx NoC No No
H ¨ubener et al. Virtex II BM-LUT-H ¨ubner Bus No Yes
ESM Virtex II BM-Xilinx P2P restricted yes
Proposal Virtex II BM-TBUFs/LUTs Bus(P2P/P2M) Yes Yes
in the Table 2.11, it can be concluded that the characteristics of virtual architectures designed using the method proposed in this Chapter are:
1. Hard cores can be loaded dynamically in slots, with no influence to other running cores. The on-chip communication remains fully active during the partial reconfiguration process and reconfiguration is reliable.
2. Hard cores can be relocated in any slot position. For the 1D model this means that cores can be horizontally reallocated, while for the 2D model approach hard cores can be reallocated horizontally and vertically.
3. Slots can be grouped horizontally (1D and 2D model) and vertically (2D model) to allocate bigger cores without losing relocation capabilities.
4. Slots have access to on-chip specific resources. But, if the resulting architecture is not fully homogeneous, then hard cores that make use of these resources should be allocated in a proper position, next to that resource.
To summarize: virtual architectures, designed following the method presented in this Chapter, have higher flexibility, scalability, make better use of the hardware resources and provide stability during reconfiguration.
More specifically for Xilinx FPGAs, the proposed method permits to overcome the frame based reconfiguration deficiency of Virtex II and Virtex II Pro FPGA at the architecture level and permits to have relocation in 1D and 2D architectures. Also, although the method has been applied for Virtex II based FPGA, it is directly applicable to other FPGAs, for instance Virtex 4 and Virtex 5.
A specific analysis of the on-chip interconnections has been made. Table 2.12 includes a summary of the features of two bus based on-chip communications infrastructures from
2.5 Results 61
the state of the art, described in section 2.1.2, and the two, also bus based, presented in section 2.4.4: the Bus-v1 for an XC2V1000 and the improved Bus-v2 for an XC2V3000 FPGA.
From the data included in Table 2.12, it can be concluded that the Bus-v2 based system has the highest flexibility (relocation possibilities) and integration (more wires in less CLB rows). Compared with the rest solutions, Bus-v2 has more communication wires (Num. Wires = 50) integrated in less area (Used Chip Rows = 4). Also, the frequency and delay results are good (Device freq. and End to end delay in Table 2.12). It is important to mention that the H ¨ubner and Moraes et al. data has been taken from [MHB04b] and [PdMM+02] respectively, while for Bus-v1 and Bus-v2, data has been measured with an oscilloscope (frequency) or using the FPGA Editor tool (end to end delay).
Table 2.12:Bus communication infrastructures comparison
Moraes et al. Bus-v1 (section 2.4.4) H ¨ubner et al. Bus-v2(section 2.4.4)
Device Virtex E XC2V1000 XC2V3000 XC2V3000
Num. slots 2 6(real 4) 4 8(real 6)
Slotwidth NA 4 8 6
Num. Wires 7 12 48 50
Used Chip Rows 4 1 (2.5 %) 6 (9.3 %) 4 (1.5 %)
Data width 1 4 16 16
Used resources 0 Slices 32 Slices 80 Slices 144 Slices
24 TBUFs 20 TBUFs 0 TBUFs 112 TBUFs
End to end delay NA NA 5.5 ns 4 ns
Device freq. NA 60 MHz 66 MHz 75 MHz
Relocation no yes no yes
Reference [PdMM+02] NA [MHB04b] [KJdlTR05]
NA - data Not Available
More in detail, two main factors, listed next, are involved in the achieved higher integration (lower area overhead) of the designed communication structure:
• One of the main advantages of using CLBs as interconnection resources is the possibility of allocating more than one communication structure of this type in one row (advantages have been summarized in Table 2.8). A CLB bus macro with eight wires can start or end in each used CLBs. For instance, if a slot is six CLB columns wide, then up to 48 wires can be allocated in a single row. This property has been widely exploited for building a 2D NoC based reconfigurable system which will be described in Chapter 3.
• The combination of TBUFs and CLB routing resources.
The frequency achieved in Bus-v2 is around 14% higher than the H ¨ubner et al. version, and 25% higher compared to Bus-v1. This is due to the reduced amount of used slices as