The slots definition, originally presented next, leads to the design of flexible VAs.
1. All slots in a reconfigurable system have to be equal in terms of shape, composition and size. In the case of Virtex II and Virtex II Pro FPGAs, for achieving maximum homogeneity, slots can be based only on CLB columns.
BRAMs, MULs, DCMs and other specific elements are not considered part of a slot, they are separate elements.
2. Slot boundaries have to be defined such that hard cores allocated in them have access to on-chip specific resources, BRAMS and MULs.
3. A slot does not span the entire FPGA height or all the FPGA rows in a reconfigurable region (for Virtex 4 and Virtex 5). Slot boundaries are restricted by the communication structure borders. This facilitates hard core relocation.
4. A slot accesses the on-chip communication structure only through specially defined for that access points. Access points have to be placed in the same position relative to the slot borders, for all slots. This permits relocations.
With the previously presented slot definition, architectures with 1D and 2D slots distributions have been defined in the next paragraphs for Virtex II and Virtex II Pro FPGA families.
In order to divide a reconfigurable area into slots, first some parameters related to the FPGA capabilities, in the context of reconfigurable systems, have been defined in Table 2.1 and will be further used.
The amount of slots that can be defined in a reconfigurable area and the slots size SlotSize) depends on the target FPGA available logic resources. Therefore, the slots size is defined by slots width - SlotWidth and slots height - SlotHeight and are measured in CLB Columns and CLB rows respectively.
Usually, in virtual architectures with one dimensional resource division, the on-chip communication infrastructure is allocated in the FPGA top or bottom part. Example 1D based architectures, where the communication structure occupies the bottom part of the FPGA, can be seen for Virtex II FPGAs on the left side of Figure 2.14, and for Virtex II Pro
2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method 45
Table 2.1:FPGA Virtual Architecture Definition Parameters
Parameter Definition
chipCLBCols Number of device CLB Columns chipCLBRows Number of device CLB Rows chipRAMCols Number of device BRAM column
fixedCLBCols Number of CLB columns occupied by the fixed area
Number of CLB rows occupied by the communication structure fixedCLBRows
(for 2D VAs this value is per slot row)
fixedRAMCols Number of BRAM columns occupied by the fixed area chipPPCs Number of embedded microprocessor in the device
N Number of CLB columns between two BRAM columns
S Number of slots in the virtual architecture SClos Number of slot columns in the virtual architecture SRows Number of slot rows in the virtual architecture
FPGAs on the right side. It is worth pointing out that with Virtex II Pro devices a more regular structure, where there is a BRAM column next to each slots, can be achieved.
However, due to the PPCs, there are at least twelve CLB columns that are additionally assigned to the fixed area, see Figure 2.14. On the contrary, for virtual architectures that follow a two dimensional resource division, the communication structure is allocated along the FPGA device. There are two communication channels defined per slot row, one on the slot top and other on the bottom, permitting each slot to be connected to as much slots as possible. A general view of a 2D model can be found on the left side of Figure 2.15, while its general mapping on a Virtex II with two rows can be seen on the right side.
A set of relations have been identified, based on the described slots distribution and using the definitions included in Table 2.1. These relations permit to calculate different combinations of number of slots (S) to slotSize (S/slotSize), which can be further used during reconfigurable system design for selecting the most appropriate combinations, depending on the target application. Relations for Virtex II FPGAs, valid for both models can be found in Table 2.2, while for Virtex II Pro they can be found in Table 2.3.
Based on the relations presented in tables 2.2 and 2.3, some S/slotSize combinations have been calculated and can be found for Virtex II in Table 2.4 for 1D slot distribution, and in Table 2.5 for the 2D distribution. For Virtex II Pro, the S/slotSize combinations can be found for 1D and 2D in tables 2.6 and 2.7 respectively. For Virtex II FPGAs, slot widths that result in slots sizes bigger than 70 CLBs have been taken into account and have been included in the tables. On the contrary, for Virtex II Pro FPGAs, the selected slot width is constant, slotWidth = N, because these FPGAs have more regular BRAM distribution. Additionally, depending on the selected application it could be recommended to include some BRAMs in each slot if the slots equality is preserved.
46 2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method
BRAMs Access Point
Virtex II
Sl ot
Fixed area
Virtex II Pro
Figure 2.14: One dimensional general virtual architecture for Virtex II FPGA families on the left and for Virtex II Pro on the right.
S:01 S:11 S:21 S:31 S:41 S:51 S:61 S:71
S:01 S:10 S:20 S:30 S:40 S:50 S:60 S:70
BRAMs Access Point Virtex II Slot
Slot
Slot Slot
Fixed area
Figure 2.15: Two dimensional virtual architecture general view on the left and an example mapping for Virtex II on the right.
Regarding the communication structure occupied area, for the 1D approach it has been defined to be four rows (fixedCLBRows = 4). It is important to notice that the communication structure area is reserved for the on-chip communication implementation. This permits to achieve hard core relocation and stable reconfiguration (two of the defined requirement). For the 2D slot distribution tables 2.6 and 2.7, the communication structure occupied area has been defined to be eight CLB rows, (fixedCLBRows = 8), four for the bottom slot channel and four for the top channel. For
2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method 47
Table 2.2:Virtual architectures design relations for Virtex II FPGAs.
Parameter Value
N chipCLBCols − f ixedCLBCols − 2
chipRAM Cols − f ixedRAM Cols
SClos N ∗ (chipRAM Cols − 2)
SlotW idth , 4 ≥ SlotW idth ≤ N SRows 2, 4, 8...,
S SClos ∗ SRows
slotWidth 4, 6, 8...,
slotHeight chipCLBRows
SRows − f ixedCLBRows fixedCLBRows 4, 8..., chipCLBRows
Table 2.3:Virtual architectures design relations for Virtex II Pro FPGAs.
Parameter Value
N 6
SClos N ∗ (chipRAM Cols − 2ChipP P Cs − 1)
SlotW idth , for 1D
SClos N ∗ (chipRAM Cols − 1) SlotW idth , for 2D SRows 2, 4, 8..,
S SClos ∗ SRows
slotWidth N, 2N, 4N...
slotHeight chipCLBRows
SRows − f ixedCLBRows fixedCLBRows 4, 8..., chipCLBRows
example, following a 1D model, the possible amount of slots that can be defined in an virtual architectures that target an XC2V3000 FPGA is 4, 8 or 12 (S = 4|8|12 in Table 2.4).
The slots width related to each possible amount of slots is 12, 6, or 4 CLBs respectively (SlotWidth = 12|6|4 in Table 2.4). The slots height is 108 CLBs and therefore the resulting slot size in CLBs is 720, 360 or 240 respectively ( SlotSize = 720|360|240 in Table 2.4). The same system is used all the FPGAs and for Table 2.5.
48 2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method
Table 2.4:Virtual architecture slots distributions for Virtex II - 1D Model
Device Parameter
XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000
LC 1M 1.5M 2M 3M 4M 6M 8M
chipCLBRows
XchipCLBCols 40X32 48X40 56X48 64X56 80X72 96X88 112X104
chipBRAMCols 4 4 4 6 6 6 6
BRAMs per Col 10 12 14 16 20 24 28
N 12 16 20 12 16 20 24
S 2|4 2|4|8 2|4|10 4|8|12 4|8|16 4|8|20 4|8|16|48
SlotWidht 12|6 16|8|4 20|10|4 12|6|4 16|8|4 20|10|4 24|12|6|4
SlotHeight 36 44 52 60 76 92 108
SlotSize(CLBs) 432|216 704|352| 1040|520| 720|360| 1216|608| 1840|920| 2592|1296|
176 208 240 304 368 648|432
LC Logic Cell
Table 2.5:Virtual architecture slots distributions for Virtex II - 2D Model Device
Parameter
XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000
LC 1M 1.5M 2M 3M 4M 6M 8M
chipCLBRows
XchipCLBCols 40X32 48X40 56X48 64X56 80X72 96X88 112X104
BRAMCols 4 4 4 6 6 6 6
BRAMs per Col 10 12 14 16 20 24 28
N 12 16 20 12 16 20 24
S 2|4 2|4 2|4 4|8|12 4|8|16 4|8 4|8|16|48
SRows 2 2 2 2 4 4 4
SlotWidht 12|6 16|8 20|10 12|6|4 16|8 20|10 24|12|6|4
SlotHeight 12 16 20 24 12 16 20
SlotSize(CLBs) 144|72 256|128 400|200 288|144|96 192|96 320|160 480|240|
120|80 LC Logic Cell
2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method 49
Table 2.6:Virtual architecture slots distributions for Virtex II Pro - 1D Model Device
Parameter
XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100
LC 11M 20M 30M 43M 53M 74M 99M
chipCLBRows
XchipCLBCols 40X34 56X46 80X46 88X58 88X70 104X82 120X94
BRAMCols 6 8 8 10 12 14 16
BRAMs per Col 8 12 18 10 12 14 16
PPCs 1 2 2 2 2 2 2
N 6 6 6 6 6 6 6
S 3 3 3 5 7 9 11
SlotWidht 6 6 6 6 6 6 6
SlotHeight 36 54 76 84 84 100 114
SlotSize(CLBs) 216 324 456 504 504 600 684
LC Logic Cell
Table 2.7:Virtual architecture slots distributions for Virtex II Pro - 2D Model Device
Parameter
XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100
LC 11M 20M 30M 43M 53M 74M 99M
chipCLBRows
XchipCLBCols 40X34 56X46 80X46 88X58 88X70 104X82 120X94
BRAMCols 6 8 8 10 12 14 16
BRAMs per Col 8 12 18 10 12 14 16
PPCs 1 2 2 2 2 2 2
N 6 6 6 6 6 6 6
S 4 6 6 8 10 12 14
SRows 2 2 2 2 4 4 4
SlotWidht 6 6 6 6 6 6 6
SlotHeight 12 20 32 14 14 18 22
SlotSize 72 120 192 84 84 108 132
LC Logic Cell
50 2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method