EVALUACIÓN DE LAS AMENAZAS

There are two main types ofccd array imagers: the full frame transfer and the interline imager [38]. In the full frame transfer array, there is an optically exposed area for image

3.5. Circuit Structures 65

(a) (b)

Figure 3-20: Energy band diagram for buried channel ccd with (a) no charge, and (b) with charge.

W1 W3/4

W1/2 W0 W1/4

y

Potential

Figure 3-21: The potential into the semiconductor for a buried channelccdwith 0, 1/4, 1/2, 3/4, and full charge. After [37].

P2 P4

P1 P3

Potential

SCCD

BCCD

E−field

Figure 3-22: Burying the channel leads to smoother fringing elds enhancing transfer e-ciency.

acquisition, and an area covered by a light shield. After acquisition, the entire image frame is transferred into the protected area, and then is typically read out serially while another image is acquired. The main advantage of this technique is that the ll factor (how much of the pixel area is devoted to gathering the charge generated by photons) of the im-ager can approach 100%. In the foe chip, we require not one but two images in order to compute the brightness gradients using rst centered dierencing as shown in Figure 2-7. As we process data a column at a time, we need access to both images. This is dicult to provide eciently using a full-frame approach, as this requires that the two images be interleaved. It was decided to use the second type of imager structure, the interline imager as shown in Figure 3-23, since it can quite easily be made to provide the interleaving of images.

In the interline topology, we have covered shift registers running alongside the optically exposed photo-gates. Once an image has been acquired in the photo-gates, it is typically shifted into the interline shift registers and then strobed out while a new image is acquired. In our application, we merely place two stages of shift register per pixel; this provides the additional storage required to hold the rst image while the second image is acquired. After acquisition of the rst image is complete, it is placed in the interline shift registers and shifted over once in the register to the right. After the acquisition of the second image is done, it is also placed into the register and then the image pair is strobed out together. The overall size of the embedded imager, taking up 90% of the chip area, is 6

:

9

mm

6

:

9

mm

. The actual pixel size including the two stages of interline register is 108

m

108

m

, and this was driven by the pitch in the processing array downstream. This size is quite a deal larger than commercial imaging chips, which have pixels that are typically an order of magnitude smaller in each dimension. These chips also have 100 times more picture elements than the 6464 = 4096 pixels on the foe

3.5. Circuit Structures 67

Input/Output Register

Shift Transfer Gate

Polysilicon 1 Polysilicon 2

Exposed Photogates

Interline Register 2 Storage Areas Per Pixel Photo−transfer gate

Figure 3-23: Schematic representation of the interline ccd imager on thefoe chip.

chip. For example, the Sony ICX022AL-3 interline ccdimager has pixel sizes of 11

m

13

m

with 768493 = 0

:

38

M

pixels in an active area of 8

:

8

mm

6

:

6

mm

. Hence, the foe chip collects signal over a comparable area, and each foe pixel is the equivalent of100 pixels of a standardccd imager, and hence can acquire the same size charge packet 100 times faster as a result. This is what allows us to have vastly larger frame rates than standard cameras (30Hz), into the kilohertz range.

To the left of the imaging array is shown an input/output shift register running up the side where two stages per interline row are required to match the imager's pitch. This allows us to input data into the array and also take o-chip raw image data. Getting raw image data o of the chip is essential not only to quantify ideal algorithm performance, but also for calibration of the imaging parameters necessary to map the chip's 3-D motion to the resultantfoe location.

Since the I/O register was intended for testing and calibration only, it was broken up into eight separate registers, each of which has a split-gate input structure on one end and a oating gate output structure at the other end. This was done to relax the requirements on the speed of output registers.

To the right of the imager, we have an array of oating gate ampliers, with four per row as shown in Figure 3-24. Of the four outputs in a row, two are from two columns in the rst image and other two are from the same column in the second image. The four values from these ampliers, along with the four from the row above, provide the eight inputs needed for the analog processors in thecmos array to estimate the brightness gradient.

Since the process that we will be using for fabrication of thefoechip is buried channel, we need an appropriate lumped circuit model for the resulting oating gate output structure. This model is shown in Figure 3-25. Here we have a depletion capacitance

C

d2 from the channel to the substrate, as well as another depletion capacitance

C

d1 from the channel to the oxide.

From the oxide to the gate we once again have

C

ox, and loading the output gate we have

C

l = 2

C

ol+

C

i as before. The

C

d that we had in the surface channel model is now split in two, with the injection point occurring in between. Notably, the analysis is the same as before except that

C

d is replaced by

C

d2 while

C

ox is replaced by the series combination of

C

d1 and

C

ox. This results in the relation:

V

out=

Q

s

C

l

C1^d2

C1^d1 +_C¹d2 + _1Cl +_C^1ox

!

(3

:

46) Now, we typically have the inequality

C

ox

> C

l

> C

d1

> C

d2. We can once again approximate to nd:

V

out

Q

s

C

l

C1^d2 C1^d1 +_C¹d2

!

=

Q

s

C

l

C

d1

C

d1+

C

d2

(3

:

47) Even though

C

d1

> C

d2, we leave their terms in place as

C

d2 may be as much as 30% of

C

d1

leading to a gain reduction of perhaps 25%. Typical sensitivity for this structure is on order 0

:

75^;1

:

5

V=e

^;. This equation would seem to imply a fair amount of nonlinearity due to the

3.5. Circuit Structures 69

Interline CCD Shift Register From

Imager

Vbias Vbias Vbias Vbias

Vout1 Vout2 Vout3 Vout4

Output Diode

RG RG RG RG

VR VR VR VR

Inter P1 Inter P2 Inter P4

Figure 3-24: Estimating the image brightness gradients requires four oating gate outputs in a row.

n−Si

p−Si

Oxide Signal Charge Depletion Region

Depletion Region Depletion Region

Cox Cd1

Qs

Col Col

P2 P4

Cd2 Vout

Vdd RG

VR

A ∆Vout Ci

Figure 3-25: Lumped circuit model for the oating gate output structure in a buried channel ccd .

variation of the depletion capacitances; in practice the nonlinearities of

C

d1and

C

d2tend to be similar in nature, and the transduction is still quite linear [7].

In document Planeación Estratégica para la Cooperativa de Ahorro y Crédito “General Ángel Flores Ltda.” (página 154-159)