EVALUACIÓN DE LAS DEBILIDADES

which results in:

=

8

>

>

<

>

>

:

;1 if

^;1

^p2^;

² if

²

<

1

1 if

1 (3

:

56)

A graph of this function is shown in Figure 3-28. Near the origin, the curve appears quite linear, with a normalized transfer characteristic of

^p2

(3

:

57)

The required four input transconductors for brightness gradient estimation are shown in Figure 3-29 along with the appropriate cascoded mirroring to form the desired linear com-binations of Equation 3.51. Recall that the input dierential voltages on these pmos source coupled pairs come from the outputs of the oating gate sense ampliers from theccdsection.

Using the approximate numbers of

Q

max = 1

Me

^; with oating gate sensitivities of 1

V=e

^;, we expect input signal swings to be on order 1

V

. Hence, we can set the input range of the source-coupled pairs

V

r to match the output signal swing from the oating gate ampliers.

Since we use an

n

-well process, we can tie the back gates ofpmosdevices to their respective sources. This eliminates the back-gate eect, which causes the threshold voltage of the devices to vary with

V

sb, the source to back-gate voltage. Additionally, due to the reduced mobility of holes compared with electrons, pmos devices are 2{3 times more resistive than nmos devices for the same channel length. This means that, with the same gate geometry and bias current, a pmoschannel source coupled pair will have a larger active range than annmos source coupled pair. Thus, we usepmos source coupled pairs. For the Orbit process,

=

C

ox

=

225

A=V

² for

n

-channel devices and 10

A=V

² for

p

-channel devices. With a current of

I

= 5

A

, this requires thepmosdevices in the source-coupled pair to have

W=L

= 0

:

5 = 6

m=

12

m

. On the chip, the biasing current sources

I

are implemented using standard improved cascode current sources [50].

3.5. Circuit Structures 75

I I I I

Bias

Bias

Bias V(i+1,j+1,k+1)

V(i,j,k)

V(i+1,j,k+1) V(i,j+1,k)

V(i+1,j,k)

V(i,j+1,k+1) V(i,j,k+1)

V(i+1,j+1,k)

∆ ∆

∆ ∆

∆ ∆

2I +2 Ix 2I −2 Ix

2I +2 I_y 2I −2 I_y

2I +2 It 2I −2 It

Figure 3-29: Using transconductors and mirrors to generate the rst centered dierence ap-proximations to the image gradients.

From Input Trans−

conductors 8 2

Absolute Value Circuit Loads

to form I_t

Timing

W

Latch Row Mask Bit

Row Mask Bit

Pass Gate

∆ t

|2 I |

∆t

|2 I |

η 2I

∆ t

− |2 I | η 2I

Off−chip

Figure 3-30: Block diagram representation of the Cuto Weighting Function.

2I 2I

φ φlatch

φreset reset

φlatch

φlatch

Vreset Vreset

W Mask Mask

∆

2I +2 I_t 2I −2 I∆ _t

∆ t

− |2 I | η

2I 2Iη

E_t

| |Bus

S

_abs

Off−chip:

Figure 3-31: Circuit implementation of the Cuto Weighting Function.

From Previous Stage

φ

φ φ φ

φ

To Next Stage

Mask Mask m1

φm1 sm1

φm1

φm2 m2

φmr

φmr

φmr

φmr m2

m2

Figure 3-32: One stage of the masking shift register.

3.5. Circuit Structures 77 of the^j2

I

t^jsignal is made and sent o-chip through a mask-bit controlled pass gate. The full circuit implementation for the cuto weighting function is shown in Figure 3-31.

The

E

t current

I

tis dierential and balanced, so we can represent it by:

I

+ = 2

I

+ 2

I

t

I

^; = 2

I

^;2

I

t (3.59)

The two current sources of size 2

I

subtract the bias current o of

I

+ and

I

^;. The remaining current ows through the double diode-connected nmos transistors if it is positive. Thus, if

I

t

>

0, the right double diode will carry the current 2

I

t while the left double diode will carry no current. Similarly if

I

t

<

0, the right double diode will carry no current and the left double diode will have ^;2

I

t. We mirror o these two currents and add them together. The resulting current is^j2

I

t^j, as desired. An extra copy of^j2

I

t^jis easily obtained by duplicating the current mirrors; this signal is sent through a pass transistor controlled by the complement of the mask bit and from there o-chip for the absolute value channel.

We now subtract this^j2

I

t^jcurrent from a reference current 2

I

as shown. If the resulting current is positive, then ^j

E

t^j

<

and

W

should be low. If the resulting current is negative, then^j

E

t^j

>

and

W

should be high. We feed this current dierence into the latch at the right of the diagram. While the reset signal

reset is high, the reset transistors pre-charge the nodes of the latch to a voltage

V

reset. During this time, the signal current ows into the latch and out of the left reset transistor. When the reset signal goes low, the comparator input current is integrated onto the left parasitic capacitor of the latch, forming a voltage dierence across the latch. When the latch signal

latch goes high, the latch amplies the voltage dierence to the rails. Since this comparator is not driven dierentially it will exhibit oset. However, this merely changes the eective value of

. To minimize this oset, the complimentary signals

latch and

latch can be driven with controllable rise and fall times.

A pull-down at the input to the latch and driven by the masking bit is provided. When this bit is asserted, one side of the latch is always pulled down, and the latch evaluation will always result in

W

= 1, eectively masking out the processor. One stage of the masking shift register used to shift in the mask bits is shown in Figure 3-32. It is a simple modication of a standard static latch based structure, employing 2-phase non-overlapping clocking [51]. It is composed of two identical sub-blocks, each one driven by one of the phases, and each of these sub-blocks consists of an inverter pair with some pass gates. When the appropriate clock phase is not active, the two inverters are closed in a feedback loop. When the phase is active, the feedback loop is broken and the input from the previous substage is driven in. The reset transistors force a logic 0 into the inverter pair when

reset is asserted. This has the eect of setting all the mask bits up and down the register to zero, indicating that no processors are masked out in the computation. This is intended to be the normal mode of operation.

Now that the cuto weighting decision has been made, we need to apply it to the image

gradients. The circuit for doing so is shown in Figure 3-33. In this circuit structure, we take the currents

I

x

; I

y, pass them through a pass transistor controlled by the weighting function decision, and into a

p

-channel cascoded current mirror sized 2:1. This accomplishes the weighting function, and we make three copies of the resultant binary weighted currents. One copy is used for the squared gradient magnitude, while the other two are used in the multiplier core.

In document Planeación Estratégica para la Cooperativa de Ahorro y Crédito “General Ángel Flores Ltda.” (página 163-168)