8. EVALUACIÓN FINANCIERA
8.2. EVALUACIÓN ECONÓMICA DEL MODELO DE INVENTARIOS APOYADO EN EL PRONÓSTICO
Address Latch Timing Register Address Latch Timing Register Address Latch Timing Register
The Address Latch Timing Register delays initial address decode by 1 clock until the first rising clock edge after the cpu_ale asserts. This mode pipelines the address decode such that 50MHz and faster systems have ample setup time to properly select a register/memory before a synchronous clock edge. At reset, the default is to take the delay. Thus systems that are running at less than 50MHz must reprogram the Memory Controller Address Latch Timing bit to “decode address” so that performance is increased. The address latch times with fast and slow decode settings are shown in Figure 2.3 and in Figure 2.4 on page 2-3.
Region G Turnaround cycle(s) of region Region G Region H Turnaround cycle(s) of region Region H Region I Turnaround cycle(s) of region Region I Region J Turnaround cycle(s) of region Region J Region K Turnaround cycle(s) of region Region K Region L Turnaround cycle(s) of region Region L Region M Turnaround cycle(s) of region Region M Region N Turnaround cycle(s) of region Region N Region O Turnaround cycle(s) of region Region O
TA(1)
(MSB) TA(0)
(LSB) Turnaround
cycle(s)
0 0 0 cycle
0 1 1 cycle
1 0 2 cycles
1 1 3 cycles (default)
Table 2.6 Width Encoding of Bus Turnaround Cycles
Field Definition
Table 2.5 Bus Turnaround (BTA) Control Register Field Descriptions (Part 2 of 2)
cpu_masterclk
cpu_ad[31:0]
cpu_ack_n
cpu_cip_n cpu_last_n
T recovery
T data T addr T data
Data Addr Data
T TA
RC32364 Bus Interface Address Latch Timing Register
Notes
Figure 2.10 Address Latch Timing Register
Arbitration Register
The Arbitration register is used to select the arbitration method used for prioritizing access to the CPU bus by the CPU, the PCI bridge and the DMA controller channels. For the specific details of this operation, refer to Chapter 7, "DMA Controllers."
Figure 2.11 Arbitration Register Field
Bit Field Name Description
31:3 Reserved 2 DRAM Controller
Address Latch Timing
1 Memory Controller Address Latch Timing
0 IP Register Controller Address Latch Timing
Reserved to 1 to delay the address decode by 1 clock.
Table 2.7 Address Latch Timing Bit Field Descriptions
Value Description
1 Round Robin arbitration 0 Fixed Priority arbitration (default)
Table 2.8 Arbitration Field Values and Action Description
IP Controller Address Timing Memory Controller
Address Latch Timing DRAM Controller
Address Latch Timing Reserved
31 3 2 1 0
Setting Bus Frequency
1 Delay address decode by 1 clock for sys-tems running at > 75 MHz
0 Don’t delay address decode by 1 clock, for systems running at ≤ 75 MHz (default)
Setting Description
1 Delay address decode by 1 clock, for sys-tems running at ≥ 50 MHz (default) 0 Decode address on falling edge of ALE, for
systems running at < 50 MHz
0
31 1
Round Robin vs.
Fixed Reserved
RC32364 Bus Interface Address Latch Timing Register
Notes
BusError Control RegisterThe Bus Error register stores the current address of any transaction—Read, Write, CPU generated, DMA generated, or PCI generated. Bus errors occur if a bus time-out occurs and no memory space is selected. For CPU generated transactions, the RC32134 will assert the buserr_n to the CPU and will termi-nate the transaction.
RC32134’s BusError register is similar to the RC32364 on-chip Bus Error Address Register, and for CPU generated transactions, the value should be the same in both registers. The RC32134 Bus Error Register is also used on DMA operations and bus time-out errors. The Interrupt Pending Register is used to first determine whether an error occurred as a result of a bus error (non-decoded address) or a bus time-out (acknowledge never returned). The default value of this register is 0x0000_0000. The fields of the BusError register are shown in Figure 2.12. The function of each field is listed in Table 2.9.
Figure 2.12 BusError Control Register Fields
Bits Field Name Description
31:7 Reserved to "0" For future compatibility, must be written as "0".
6 WatchDog
Enable
When WatchDog Enable is enabled, when the WatchDog Timer reaches its compare count and overflows, a warm reset will be generated to the CPU. To prevent the WatchDog Timer from generating a reset, RC32134 systems must have enough OS kernel support to occasionally zero out the WatchDog Timer Count Register or to Dis-able the WatchDog function from resetting the CPU.
5 WatchDog Reset Status
When a Warm Reset is caused by the WatchDog Timer overflowing, the WatchDog Reset Status Bit Field is set to’1’. The status bit may be reset by a software write to the register changing that bit value as a ‘0’.
4 CPU BusError Enable
If the CPU BusError Enable is set, then if the CPU BusError Timer reaches its com-pare count and thus overflows, a BusError will be generated to the CPU. This BusEr-ror is caused either by the CPU taking too long or by the CPU generating an undecodable address.
Table 2.9 BusError Control Register Field Descriptions (Part 1 of 2)
WatchDog
0 WatchDog Reset has not occurred (default)
Value Description 1 Enabled (default)
0 Disabled
RC32364 Bus Interface Address Latch Timing Register
Notes
Figure 2.13 SysID Register Fields 3 IP BusTimeOut
Enable
If the IP BusError Enable is set, then if the CPU BusError Timer reaches its compare count and thus overflows, an IP BusError will be generated to the IP Bus and if RC32134 or the CPU owns the CPU bus, a BusError will be generated to the CPU.
This BusError is caused either by DMA taking too long or by DMA generating an undecodable address.
2 CPU Source If a CPU BusError is caused by the CPU BusError Timer overflowing, then the CPU BusError Status Bit Field is set. The status bit may be unset by a software write to the register with that bit value as a ‘0’.
1 IP Source If an IP BusError is caused by the IP BusError Timer overflowing, then the IP BusEr-ror Status Bit Field is set. The status bit may be unset by a software write to the regis-ter with that bit value as a ‘0’. In the present RC32134 implementation, a CPU bus error also sets the IP BusError Status bit.
0 Read/write Type
Bits Field Name Description
Table 2.9 BusError Control Register Field Descriptions (Part 2 of 2) Value Description
1 Enabled (default) 0 Disabled
Value Description
1 CPU BusError occurred from a CPU transaction 0 CPU BusError did not occur (default)
Value Description
1 IP BusError occurred from an IP transaction 5 MHz 0 IP BusError did not occur (default)
Value Description
1 BusError occurred on a read 0 BusError occurred on a write (default)
Implementation ID / Part ID Major Revision Minor Revision
Vendor ID
31 20 19 8 7 4 30
RC32364 Bus Interface Address Latch Timing Register
Notes
Bits Field Name Description
31:20 Vendor ID Vendor is IDT (0x000) 19:8 Implementation ID/Part ID Part ID is RC32134 (0x000) 7:4 Major Revision Major revision for initial silicon is (0x0) 3:0 Minor Revision Reserved (0x0)
Table 2.10 SysID Register Field Descriptions
RC32364 Bus Interface Address Latch Timing Register
Notes
Notes
Chapter 3