“INVIERTA Y CONQUISTE EL MUNDO CON SEGURIDAD”

The control element for the JFET comes from depletion of charge carriers from the n-channel. When the Gate is made more negative, it depletes the majority carriers from a larger depletion zone around the gate. This reduces the current flow for a given value of Source-to-Drain voltage.

37 Modulating the Gate voltage modulates the current flow through the device. The unipolar field effect transistor is conceptually simple, but difficult to manufacture. Why?

Well, it is possible to make bipolar transistors outside a strictly controlled production environment such as a clean room; it is absolutely necessity for field effect transistors to be prepared in a rigidly controlled and clean environment and with strict contamination control to prevent.

3.2 JFET CHARACTERISTIC CURVES

When you take a look at the characteristic curves for the JFET overleaf you will see that for a given value of Gate voltage, the current is very nearly constant over a wide range of Source-to-Drain voltages. The control element for the JFET comes from depletion of charge carriers from the n-channel. When the Gate is made more negative, it depletes the majority carriers from a larger depletion zone around the gate. This reduces the current flow for a given value of Source-to-Drain voltage.

Modulating the Gate voltage modulates the current flow through the device.

JFET Characteristic Curve

The transfer characteristic for the JTET is useful for visualizing the gain from the device and identifying the region of linearity. The gain is proportional to the slope of the transfer curve. The current value IDSS

represents the value when the Gate is shorted to ground, the maximum current for the device. This value will be part of the data supplied by the manufacturer. The Gate voltage at which the current reaches zero is called the "pinch voltage", VP. Note that the dashed line representing the gain in

38

the linear region of operation strikes the zero current line at about half the pinch voltage

3.3 OPERATION OF JFET DEVICE

The operation of Field Effect Transistor is extremely simple. A voltage when applied to the gate, input element controls the resistance of the channel, which is the unipolar region between the gate regions.

Cross Section of Junction Field Effect Transistor

In an N-channel device, the channel is a lightly doped N-type slab of silicon with terminals located at each end. The source and drain terminals bear analogy to the emitter and collector, respectively, of a Bipolar Junction Transistor. In an N-channel device, a heavy P-type region located approximately midway on both sides of the slab serves as a control electrode, the gate. The gate is similarly analogous to the base terminal of a Bipolar Junction Transistor.

Biasing N-Channel JFET

In a properly biased N-channel Junction Field Effect Transistor (JFET) as illustrated above the gate appears as a diode junction to the source-drain semiconductor slab and is reverse biased. If a voltage were applied between the source and drain, the N-type bar would conduct in either direction because of the doping. Neither gate nor gate bias is required for

39 conduction. If a gate junction is formed as illustrated above, conduction can be controlled by the degree of reverse bias.

Illustration (a) above shows the depletion region at the gate junction. This is due to diffusion of holes from the P-type gate region into the N-type channel, giving the charge separation about the junction, with a non-conductive depletion region at the junction. The depletion region extends more deeply into the channel side due to the heavy gate doping and light channel doping.

Take a look again at the illustration (a), (b), (c) and (d) above, (a) shows the depletion at gate diode under zero bias voltage. In (b) with reverse biased gate diode, the width of the depletion region increases while (c) shows the effect of increasing reverse bias which further enlarges the depletion region. Finally in (d) further increasing reverse bias pinches-off the Source-Drain channel and conduction through the semiconductor slab ceases altogether.

The thickness of the depletion region can be increased by applying moderate reverse bias as (b) illustrates. This increases the resistance of the source to drain channel by narrowing the channel. Increasing the reverse bias as shown in (c) increases the depletion region, decreases the channel width, and increases the channel resistance.

Increasing the reverse bias VGS at (d) will pinch-off the channel current.

The channel resistance will be very high. This VGS at which pinch-off occurs is VP, the pinch-off voltage. It is typically a few volts.

It should be quite clear to you by now that the channel resistance can be controlled by the degree of reverse biasing on the gate.

Remember that the source and drain are interchangeable, and the source to drain current may flow in either direction for low level drain battery voltage (< 0.6 V). That means, the drain battery can be replaced by a low voltage Alternating Current source.