Medición de los beneficios del uso de Internet como herramienta

Optical shared memory supercomputer interconnect system (OSMOSIS) architecture

proposed by IBM [73–75] is shown in Figure 2.11. It is based on a broadcast-and-

select configuration, and provides full-duplex connection at 40 Gbps data rate. It is a 64 port optical packet switch which introduces cell switching of fixed sized pack- ets of 256 bytes known as cells. Electronic control logic is implemented by using field-programmable gate array (FPGA) to control scheduling of cells. Switching is performed by reconfiguring the optical core on a cell-by-cell basis. There are two basic modules i.e. broadcast and select modules. Broadcast modules contain trans- mitters, multiplexers, amplifiers and splitters while select modules consist of SOAs, multiplexers, demultiplexers, and receivers. Packets are buffered at the ingress of the ToR switch and are multiplexed onto a single fibre using multiplexer. Eight distinct wavelengths are multiplexed in each broadcast module and after amplifying the signal

2.5. ARCHITECTURES BASED ON SOAS

from amplifier, the signal is broadcast by using 1× 128 power splitter. There are two stages in the select module of this architecture. Two stages of eight SOAs each are used as gate elements by utilizing their on/off behaviour. First stage of SOA is used to select particular fibre of desired signal output and second stage of SOA is used to select particular wavelength of desired output receiver. The centralized controller is responsible for switching on and off behaviour of these SOAs.

Broadcast Select : x 8 1x128 Star Coupler Amplifier MUX SOA SOA SOA SOA SOA SOA SOA SOA SOA SOA SOA SOA SOA SOA SOA SOA : x 128 DEMUX

Figure 2.11. Osmosis Architecture.

FLPPR (Fast Low-latency Parallel Pipelined arbitration) crossbar scheduler algo- rithm[76] is developed that provides a parallel implementation in FPGAs and achieves 51.2-ns packet cycle time for 64 ports. Speculative transmission mechanism is used to achieve minimum latency for request - grant - transmit cycles. For speculative trans- mission, two paths from each input to a given output were used in broadcast-and- select architecture resulting a 64× 128 crossbar switch. To achieve zero packet loss, a flow-control mechanism was also adopted to prevent packet buffer overruns.

Major advantage of this scheme is the low latency of packet transmission. There are many drawbacks in this scheme. First, it is a costly design in terms of capital expenditure (CAPEX) because it uses two receiver for every output port and for each receiver, it uses 16 SOAs which are expensive devices. Second, this scheme is not scalable to build thousands of nodes of interconnect due to topology of the architecture and complexity of the centralized controller. Data vortex[5,77] is the next SOA-based

2.5. ARCHITECTURES BASED ON SOAS

architecture which targets issue of scalability. It is described below.

2.5.2

Data Vortex

Data vortex is a distributed interconnection network[5,77]. Its architecture is shown in Figure 2.12(a). It uses optical packet switching and is based on SOAs which are used as a gate switching element similar to the OSMOSIS. Its network topology is based on a banyan structure and incorporates a distributed deflection routing scheme which removes packet contention without the usage of optical buffers. The nodes are arranged in cylinder C, with height h and angle A as shown in Figure 2.12(b). Each cylinder corresponds to 1 stage of the banyan network. Each node in a cylinder

consists of 2× 2 switching elements (SOAs) which are arranged in a fully connected

directed graph. A 2× 2 SOA switch uses four couplers and is controlled by controller which controls ON/OFF switching of SOAs. FDLs are used to temporarily delaying packets during switching. Packet is routed to deflection route in case of congestion in the network. Straight lines depict injection fibres, curved lines show deflection fibres and dotted lines show control cables. Each 2× 2 switching element has 2 input fibres each from north and west and two output fibres each for south and east. The prototype design of the data vortex is presented recently[78].

The biggest advantage of this scheme is the scalability as it can be scaled to the thousands of nodes using modular architecture and SOAs can also recover power losses which occur due to multi-stage path of a packet. The major drawback of the data vortex is high end-to-end packet latency due to multi-stage architecture. FDLs can only provide limited delay and packet losses can also occur due to congestion in both desired and deflection route which is not feasible in the data centres. Bidirectional op- tical interconnect network for data centres[79] is another scalable architecture based on SOAs. Unlike to all other SOA-based architectures, bidirectional architecture pro- vides bidirectional communication. It is described below.

2.5. ARCHITECTURES BASED ON SOAS

1778 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 26, NO. 13, JULY 1, 2008

Fig. 1. (a) Illustration of a 122 12 data vortex topology with 36 interconnected (C = 3; H = 4; A = 3) and distributed 2 2 2 nodes (cylinders). Straight lines are ingression fibers, curved lines are deflection fibers, and dotted lines are electronic deflection signal control cables. (b) The banyan-like crossing pattern shows the deflection path connectivity for each cylinder.

order to maximize transmission capacity, to transparently tra- verse the network.

The data vortex topology [3] was first described in [4] and first investigated in [5]–[7], and its architecture was further an- alyzed in [8]–[11]. A 12-port data vortex prototype was imple- mented and its routing performance investigated [12]. The scal- ability of the physical layer was analyzed and demonstrated in [13] and [14], and further experimental studies of the optical dynamic range and packet format flexibility were performed [15], [16]. Sources of signal degradation in the data vortex were investigated in [17] and [18], and data resynchronization and recovery was achieved using a source synchronous embedded clock in [19]. Extensible and transparent packet injection mod- ules and optical packet buffers for the data vortex were presented in [20]. Finally, alternative data vortex architecture implementa- tions and performance optimization were explored in [21]–[23]. In this paper, we present a comprehensive discussion of the data vortex interconnection network and provide a complete review of the architectural investigations and experimental re- search. Section II reviews the topology, including a discussion of the deflection routing, network scalability, and node struc- ture. In Section III, the implementation of a fully interconnected 12-port data vortex is presented along with a proposed synchro- nization approach for recovering short packets. The interoper- ability of an injection control module with the data vortex is demonstrated as well. Section IV describes the characterization of the physical layer and its quantitative impact on the system

scalability. Section V presents both alternative architectural de- signs and performance optimization considerations at the device level for next generations of the data vortex interconnection net- work.

II. DATAVORTEXINTERCONNECTIONNETWORK

The data vortex topology [Fig. 1(a)] integrates internalized virtual buffering with banyan-style bitwise routing specifically designed for implementation with fiber-optic components. The structure can be visualized as a set of concentric cylinders or routing stages, which are cyclic subgroups that allow for de- flections without loss of routing progress. Moreover, the hier- archical multiple-stage structure is easily scalable to larger net- work sizes while uniformly maintaining fundamental architec- tural concepts [5].

A. Topology

The data vortex topology is composed entirely of 2 2 switching elements (also called nodes) arranged in a fully connected, directed graph with terminal symmetry but not complete vertex symmetry. The single-packet routing nodes are wholly distributed and require no centralized arbitration. The topology is divided into hierarchies or cylinders, which are analogous to the stages in a conventional banyan network (e.g., butterfly). The architecture also incorporates deflec- tion routing, which is implemented at every node; deflection signal paths are placed only between different cylinders. Each

Figure 2.12. Data Vortex Architecture[5].