, Murillo-Pacheco Ricardo 7

The design of the readout electronics used at the Far Detector is motivated by the expected event rate. Interactions of cosmic rays and atmospheric neutrinos with the FD occur at a rate of approximately 0.5 Hz with a noise rate of around 10 kHz at each plane side due mainly to the dark noise of the PMTs and fibre noise from the scintillator. The front-end electronics were designed to cope with this rate whilst remaining sensitive to minimum ionising particles and without encountering significant dead time. Specifically, the readout was designed to operate with a threshold of 0.3 p.e., PMT gains of order 106_{, and with a timing resolution of 3-5 ns}

to enable upward-going neutrino tracks to be distinguished from downward-going cosmics [66] [67].

3.4.1 Overview

The electronics used at the Far Detector operate in an environment where the low data rate is dominated by the detector noise. At this level, commercially available

The MINOS Far Detector 55

Figure 3.3: Schematic showing the readout electronics of the Far Detector, taken from [66].

10MHz digitisers can be shared across multiple channels, saving on cost while still providing minimal dead time. Each ADC serves three PMTs, and a schematic of the full chain is shown in Figure 3.3.

Each PMT is read out by a single ASIC: a model VA32-HDR11 chip henceforth referred to as a VA chip. Three VA chips are mounted on a single VA Front-end Board (VFB) which is located outside the PMTs’ MUX box. The VFB provides power and voltage biasing to the VA and also houses two PIN diodes that monitor the light injection system used to calibrate the PMT gain curves.

The analogue signals from the VA are sent through an ASDLite discriminator into the VA Readout Controller (VARC). A VARC contains six VARC Mezzanine Modules (VMMs), each of which houses a single ADC which digitises the output from two VFBs. Under this scheme, each ADC is responsible for 6 PMTs, each with

16 channels. Each VARC is implemented as a single VME card, and groups of three VARCs, a timing card, and a Motorola VME processor share a single VME crate. Sixteen of these crates have a capacity of 27648 channels and are used to read out the 22000 channels available to MINOS.

3.4.2 The VA chip and VA Front-end Board

The VA chip is a model VA32-HDR11 Viking chip [69] manufactured by IDE AS, Norway. It has 32 channels of preamplifiers and sample-and-hold circuitry, and a multiplexing output switch. Of these channels, sixteen are used; one for each of the PMT anodes.

Of the sixteen remaining channels, four are used to identify noise effects that occur simultaneously in all channels of the chip. Additionally, a Light Injection (LI) system is used to calibrate the PMTs for linearity and stability. The LI system is monitored using two PIN diodes per VFB whose signal is read out on a further VA channel in coincidence with the PMTs.

Three VA chips are mounted on each VFB, which is used to distribute power to the chips and control their voltage bias. The VFB also houses the discriminator used to compare the analogue output from the PMT dynode with a programmable threshold, and electronics for temperature and voltage monitoring. The VFB is used for readout only, and operates in slave mode directly controlled by the VARC upstream.

3.4.3 The VMM and VARC

Pairs of VFBs are digitised by a single ADC, with a typical response of 70 ADC/p.e., which resides in the VARC on a VARC Mezzanine Module. The VARC is responsible for the digitisation, triggering, and timing of the VA chips it controls, as well as for setting their bias voltage.

The VARC receives the PMT dynode signal, affixes a timestamp using a 640MHz FPGA TDC, and generates a hold signal for the VA. Digitisation operates on a ‘two-out-of-36’ method, where the readout only takes place if the VARC receives two

The MINOS Far Detector 57

If this condition is met, the VARC reads out each VA chip one after the other. Any dynode hits that occur during this process will be ignored, so a dead time is incurred during this phase: at 5µs per chip this is between 5 and 30 µs depending on how many of the six chips were above threshold. The output from the ADC is passed to a sparsifier which subtracts the PMT pedestal from the signal and removes any signals below 20 ADC (electronic noise is typically _{∼ 2.5 ADC [}66]). Two buffers operate alternately to collect data from the VARC and transfer it out, allowing this part of the process to run without dead time.

3.4.4 Data acquisition and triggering

Each crate contains a computer known as the Read Out Processor (ROP) which is used to extract the digitised data from the front end electronics, and these are synchronised with one another using timing cards present in each crate. Each buffer readout constitutes a single time block, and the job of the ROP is to assemble these blocks into 1 s long timeframes, and to append monitoring and calibration information as appropriate.

The ROPs are connected to further DAQ computers known as Branch Readout Processors (BRPs), of which the Far Detector has six. One master BRP instructs the others to send a given timeframe to one of a batch of Trigger Processing (TP) machines. In this manner, each TP receives one full timeframe for the entirety of the detector. Each ROP, BRP, and TP machine can buffer and queue multiple timeframes, enabling the data rate of approximately 8 MB/s to be accommodated comfortably.

On the Trigger Processor, software-based triggering is applied to each of the timeframes, using a variety of triggers. Zero bias triggers are used for data in time with the beam spill, extracting all in-spill digitisations into a single event without further processing. A number of special triggers are also available for calibration and debugging etc.

For signals outside of the spill window, the TP first sorts hits within a single timeframe into groups separated by at least 156 ns. The trigger option used for atmospheric and cosmic events is the so-called ‘4/5 plane trigger’ which requires 4 out of any 5 contiguous planes in the detector to register a hit. Other triggers are

in place searching for high energy deposition in contiguous planes, and the total number of planes hit throughout the detector.

The output from a single successful trigger can in theory contain more than one event, particularly in the ND during beam spills. It is commonly referred to as a ‘snarl’.