3.3 La escuela y la educación en valores
3.3.1 Necesidad de educar en valores en la escuela.
4.3. The Electrical Subsystem 117 sections. Analog and digital grounds are kept separate to prevent digital returns from impacting sensitive analog nodes. This was not entirely possible in certain sections of the board, however.
For example thefoechip itself does not provide separate ground returns. Additionally, theccd clock drivers' signal returns go through analog ground, as some of the clock levels are required to be precision levels, and hence are referenced to analog ground. To minimize the eects of this type of coupling, ground planes were used to reduce impedances in the return path, and sensitive measurements were delayed until the transient eects had dissipated. Analog and digital grounds were also tied together in the standard star conguration at the system power supply [75, 76].
muxing is required as well. A schematic diagram for the muxing daughter board that was constructed to allow the FCP to read rawccdoutput data is shown in Figure 4-18. A variable voltage reference
V
off is formed by the op-amp circuit to the left of the diagram. This voltage is subtracted from the input signal and injected into the main circuit. This circuit clamps the input dierence to (V
d+V
z) whereV
d is the forward drop of the Schottky diodes (0:
35V) andV
z is the voltage of the bandgap zeners, which was 1.2V using LM313s. This resulted in an output clamp range of 1:
5V. Following the clamp output, we have the required 2-to-1 muxes using ADG201HScmos switches and lastly an output gain stage of 10; the output of this stage is what we drive into the FCP ADCs. By varying the pot voltage in the variable voltage reference, we essentially scroll up and down a window of interest on the input waveform to which we have applied magnication. By placing the window nearV
dd, we can t the signal swing of theccdoutput channel entirely into the appropriate input range of the ADCs. Hence, a mode of the FCP was programmed to acquire raw image data, essential for performing camera calibration and comparing system results with algorithmic ones.Each image pair acquired and stored by the FCP in external memory requires 64642 = 8Kbytes of memory. Thus the 128Kbytes of external memory in the FCP only allowed the storage of 16 frame pairs of raw data. During a motion transient, typically many more frames are required than 16, and hence the memory on the board was expanded. A memory expansion board containing 1Mbyte was constructed using the same architecture as before. Of course, now a 16-bit address pointer is insucient and a 19-bit one was implemented instead, with the memory organized as 512K16. Since the 'E14 is a 16-bit processor, accessing the address pointer now requires two external accesses. However, the auto-increment and auto-decrement features continued to be supported, so required accesses of the pointer remain rare. With this much memory in the system, 128 image pairs (256 images) could be acquired and later transmitted through the parallel port to the host computer.
Addition of both daughter boards complicated the power supply networks substantially, and grounding proved to be a problem even though the star connection philosophy continued to be adhered to. The problem that arose was that the digital ground in the system board bounced substantially, while the memory expansion board did not bounce nearly so much. Hence, occa-sionally the auto-increment and auto-decrement feature would fail. The resultant failure mode was that the address pointer would occasionally increment erroneously. Through judicious placement of ground connections as well as pull-ups on critical signals, this problem was elimi-nated. However, when motion experiments commenced, it was observed that substantial noise from the motor system coupled into the analog sections of thefoe board, unfortunately aect-ing the measured data substantially with impulsive noise. Although the path of this couplaect-ing was not obvious, placing the star connection on the metal top of the optical table successfully eliminated this noise source, probably by providing a lower impedance return path.
Lastly, as we shall see in the next Chapter, the dark current of the foe chip was, not
4.3. The Electrical Subsystem 119
Vdd Bias RS
RV
Board Chip V+ V+
Floating Gate
Vout Vbias
Common
X 8
Figure 4-17: Output circuit for one of the 8ccd I/O channels.
V+
V−
R
D1
R
R
D2
Z1
Z2
R R
Vin
Vref
R MUX
−Voff
D Q Q R
R
10R
Vout
X 8
Start Conversion System Reset
X 4
Figure 4-18: Circuit schematic for the muxing daughter board.
Copper Plate
Clamps
PVC Tubing
Copper Tube
Water Pump Ice
Bath
Figure 4-19: Simple water-based cooling system for thefoe chip.
surprisingly, substantially larger than what should be expected from a commercialccdprocess.
As dark current dependence is exponential in temperature, the dark current varied widely with the ambient temperature in the lab, which was poorly controlled. To remedy this situation, the test setup was enhanced by the addition of a cooling system for thefoe chip, as shown in Figure 4-19. This very simple forced cold water system consisted of an ice bath with a pump.
Cold water was pumped through a copper heat sink placed in thermal contact with the chip.
This sink was basically a plate placed over the chip with a thin copper tube soldered to the side of the plate. The inow and outow PVC tubing from the pump and ice bath were clamped to this tube at either end and exited the proximal mount through two access holes in the board as shown. In practice, this simple approach resulted in a factor of 2{3 reduction in the observed dark current, as well as reduced sensitivity to lab temperature variations.