With the monitoring information, a software interlock can be implemented, which is normally set to lower thresholds than the hardwired interlock of the safety path. The software interlock has higher flexibility as it can be adjusted during operation. However, it is less reliable because the computer running the software can crash.
4.2.3 Diagnostic path
To calibrate and adjust the experiment a third path is used. The front-end (FE) chips are configured with this data to efficiently collect data.
The diagnostic path has the highest granularity on the FE chip level. This path collects information directly from the FE chip through the optical readout path. The FE includes radiation and temperature sensors, together with an ADC to monitor the supply and internal voltages of the chip. These values can be transmitted together with the normal physics data. A fixed fraction of the output frames is reserved for the status information, which makes about 2 % of the data [5].
The data is transmitted optically to the off-detector data acquisition system, as de- picted in Figure 4.4 on page 41. The optical interface of the data acquisition system has to separate the diagnostic information from the physics data and send it to the detector control station. Scans are performed additionally during calibration periods to re-tune the FE for optimal data taking [5].
4.3 Control of a serial power chain
New approaches are required to control and monitor a serial power (SP) chain. See section 2.3.3 for a description of the serial power concept. For full control, it is required to power on/off individual modules in the SP chain, without disturbing the other modules of the same chain.
The LV power supply can only act on the entire chain. To deactivate individual mod- ules, an alternative current path is needed so that the remaining modules can continue to operate. Such a bypass adds the flexibility to remove single modules from the chain although adds complexity and risks. See Chapter 7 for more on the risk analysis.
DCS Controller Power (Vcan) Sensor bias (HV) To DCS computer PSPP chip power (Vdcs) Vn Vn-1 Vn-2 V2 V1 0V To Readout FE power (LV) DCS Controller Interlock Mn FE FE FE FE Mn-1 FE FE FE FE PSPP Chip PSPP Chip PP0 From Readout Type 0 services ~1.5m Type 1 services PP1 Type 2 services PP2 Type 3 services Electronics cavern ITk detector volume Type 4 services PP3 Experiment cavern ~50m ~40m ~15m ~6m Mn-1 FE FE FE FE Mn-1 FE FE FE FE PSPP Chip PSPP Chip CAN inter- face
Chapter 4 Detector control system Development of a DCS Chip
There are two chips planned for implementing the monitoring and control of an SP chain [5]. The pixel serial powering & protection (PSPP) chip which is the front-end element for the control & feedback path. The second chip, which acts as a bridge between the off-detector electronics and the PSPP, is called DCS controller [87]. Figure 4.6 on the previous page shows the chain with the DCS ASICs.
4.3.1 DCS controller
The DCS controller is placed on patch panel 0 (PP0) located at the end of a mechanical structure for the modules of one or multiple SP chains. The electronics cavern houses the power supplies and off-detector electronics for the detector control station. Between the electronics cavern and PP0 are about 100 m of cables. This requires a driver strong enough to transmit the data and a protocol for reliable operation. The controller area network (CAN) was chosen for the high reliability and low line count. The CAN stan- dard [89] implements a cyclic redundancy check in the messages and resolves conflicts. To transmit data a bidirectional differential pair is used and multiple nodes can be connected in a bus to further reduce the lines.
A prototype with a CAN node was developed in Wuppertal [90]. Since then the requirements for the DCS controller were updated. The application layer CANopen will be used to simplify the integration of the DCS controller in WinCC. CANopen is already used in ATLAS DCS and other LHC experiments to implement monitoring [91]. Per SP chain will be one serial control bus (SCB) connecting up to 16 PSPPs together. The SCB is a bus developed at Wuppertal for AC coupled nodes (see section 5.4). The DCS controller is the master of the SCB. A block diagram of the DCS controller is given in Figure 4.7.
The DCS controller includes also an ADC for monitoring the temperature on PP0. This ADC would be also used to monitor the status of the DCS controller itself. The oscillator is used to create the clock required for CAN and SCB.
4.3.2 PSPP chip
The PSPP chip is the front-end element of the control & feedback path. This chip includes the bypass and monitoring for individual modules. It is explained in detail in the Chapter 5. SCB Master CAN node CANopen (bridge logic) I/O I/O Regulator
Oscillator MonitoringADC
Figure 4.7: Block diagram of the DCS controller.
Chapter 5
Pixel Serial Power & Protection chip
The pixel serial powering & protection (PSPP) chip is an ASIC designed for the ATLAS ITk Pixel detector control system (DCS). It is the front-end element of the control & feedback path described in section 4.2.2.
Its main purpose is to control and monitor a single module in a serial power (SP) chain. A bypass transistor is integrated, which allows deactivating a module. This bypass provides a low-resistive alternative path for the LV supply current.
The PSPP chip operates in parallel with the pixel module and therefore shares the same ground potential. On the other hand, it must be powered independently of the pixel module to operate in times when the front-end (FE) chips are switched off. This requires a power scheme that allows supplying all PSPPs of one SP chain together. Further, flexibility is required to operate with different configurations of the chain. The reference potentials of the modules and thus PSPPs changes with the LV supply current and the number of bypasses active.
The development of the PSPP chip towards a possible production is the main goal of this thesis. First, the requirements are presented, based on the ATLAS Pixel technical design report [5]. Afterward, the development of the PSPP chip and its function are described.
5.1 Requirements
The main tasks of the PSPP are the following: • Operation in a serial power chain
• Independent communication and power lines
• Monitor the operating voltage of the pixel sensor module with a precision of 10 mV • Monitor the module temperature with a precision of 0.5 K
• Switching individual modules in the serial chain • Operation in a highly radiated environment
The independent service lines are required to operate the PSPP even when the FE chips are switched off. The temperature monitoring provided by the PSPP is also required during shutdowns for information about annealing of the sensors. To keep the number of services low, a common supply together with a communication bus for all PSPPs in a serial power chain is used.
Chapter 5 Pixel Serial Power & Protection chip Development of a DCS Chip
Based on this, the following requirements are set for the PSPP:
• The PSPP must be able to bypass the maximal supply current of 8 A.
• The switching of the bypass should not create current transients of more than 5 %. • After power-up or in case of power loss the bypass should remain open.
• The bypass can be controlled remotely by command.
• Automatic activation of the bypass in case of over-voltage (OV) or over-temperature (OT). This feature can be disabled.
• The module voltage, temperature and internal values are monitored and digitized by the PSPP.
• Negative temperature coefficient (NTC) resistors are used as temperature sensors. The power for them is provided by the PSPP.
• The SP has to be qualified for 16 modules. Therefore up to 16 PSPP chips have to operate in one chain.
• The PSPP will be located on the type 0 services (see Figure 4.6 on page 43) to include the possibility of bypassing an open module connector.
• The communication bus should be able to operate with lines of 2.5 m length. • The communication lines have to be AC coupled for operation with independent
ground potential of each chip in a chain.
• The total power of the PSPP should be as low as possible to work without active cooling in all operation modes.
• As the chip is located close to the pixel modules, the PSPP must have the same radiation hardness as the FE chips.
• Operation in a high magnetic field of 2 T.
• Operating temperature range between (−40 to 40)◦C.
The radiation levels listed in Table 5.1 were defined for the FE chip [92] and are therefore also applied to the PSPP. The single event upset (SEU) rate is given for all PSPP chips in the detector.
The number of bypass activities due to SEU should be kept as low as possible. One per month in the entire detector is acceptable for operation. Such an event would require
Table 5.1: Radiation tolerance requirements for the PSPP.
Parameter Value
Total ionizing dose 500 Mrad
Non-ionizing fluence 1 × 10161 MeV neqcm−2
Flux of >1 GeV particles <2 × 108cm−2
Charged particle fluence 150 × 10−3cm−2pp−1
Hadrons >20 MeV fluence 85 × 10−3cm−2pp−1
SEU rate for bypass <1 /month