The internal registers of the PSPPv4 were read out during the irradiation at the PSI. They were read every 2 s and the configuration registers (bypass and bandgap trimming) written every 5 or 10 s. The writing of the registers was done to make sure, that the chip stayed operational and to reset it if any upsets should occur. In total the PSPPv4 received a dose of 1.9 Mrad.
Read/write and constant registers
The registers of the PSPPv4 chip are listed in Table 5.5 on page 66. Register 0,1 are constants and were always read correctly. The status register (nb. 4) is defined by
Chapter 6 Operation and performance measurements Development of a DCS Chip
external signals and was also always read the same. A non-expected value in these registers could indicate a bit flip in the communication logic, which never happened.
All bits in the digital output register were set either to ‘1’ or to ‘0’. When reading back this register, only these two values were read. The same for the bandgap trimming registers (nb. 10-12) which were always written and read back at the default value.
All these registers are protected by triplication. No SEU was observed in these registers indicating the correct operation of the protection. The total fluence observed by the PSPPv4 during the test beam was 3.42 × 1013p/cm2. From the trimming and status
register, the SEU cross-section for the triplicated bits has to be <1.5 × 10−15cm2.
Bypass register
The bypass register is the most critical register in the PSPP. As described in section 5.5.2, the bypass can be set from three different sources: first by command, second by an over- voltage and third by an over-temperature. The automatic over-temperature protection was switched off during the irradiation at the proton irradiation facility while the over- voltage protection was left activated.
There were some unexpected values read-back from this register, where mainly the over- voltage (OV) and over-temperature (OT) flags were activated. The voltages measured at the input of the comparators were during all these events far from the threshold voltage. Figure 6.11 shows two example events where the OV and OT flags were activated. The OV flag was activated once, while the OT flag was set five times. Another event looked like the chip was reset, as all registers including the bypass register went to the default value.
The suspicion is that a SET happened in the comparator. The comparators are not triplicated and connect to an asynchronous set input of the flip flops storing the flags. Therefore a transient on the comparator output could upset the flags. It should be
2019.02.02 04:47:45 2019.02.0204:47:50 2019.02.0204:47:55 2019.02.0204:48:00 2019.02.0204:48:05 Date 0.45 0.50 0.55 Voltage [V]
Over temperature flag
Temp0 Temp1 ThTemp Bypass Reg 0x08 0x48 Register value (a) 2019.02.02 01:17:25 2019.02.0201:17:30 2019.02.0201:17:35 2019.02.0201:17:40 Date 0.00 0.25 0.50 0.75 Voltage [V]
Over voltage flag
V_by ThMod Bypass Reg 0x89 0xA9 Register value (b)
Figure 6.11: Possible single event transient (SET) in comparator activating the OT flag (a) and OV flag (b). Normally the Temp0 or Temp1 voltages should be below ThTemp, respectively V_by larger than ThMod to activate the flags.
6.3 Irradiation tests
reminded that the PSPPv4 has two comparators for temperature. The two outputs are combined with a logic OR as described in section 5.5.2. Therefore it is normal that the OT flag is activated more often. Furthermore, the same comparator circuit is used in the power-on reset. This could therefore also cause a reset in the chip.
Nevertheless the observed flags, the bypass was never switched unintentionally during the entire irradiation campaign. The command bit used for manual activation and the enable bits are therefore properly protected.
Simulation of the comparator regarding single event transients
A simulation was performed to verify if an SET in the comparator could indeed cause an upset of the flag. This was done based on the methods described in section 3.1.5 and with parameters from [59].
Figure 6.12 shows the simplified schematic of the test bench used. The complete comparator schematic was used, but with an ideal voltage source for the supply voltage. Additionally, the logic for the over-voltage flag was added at the output. A charge pulse was injected into the two nodes X and X to simulate a hit in a transistor from the logic gates.
Figure 6.13 on the next page shows the result of the simulation. The top graph shows the current pulses induced in nodes X and X. The first pulse is on node X, while the second pulse on node X. The second and third graphs show the voltage at node X and node X respectively. The fourth graph is the output of the comparator and the last the status of the OV flag. The colors represent the amount of charge injected. Red is a pulse of 100 fC, green corresponds to 40 fC and blue to 10 fC. Similar values were also used by [59] and correspond to a particle with an effective LET of about 2 MeV cm2mg−1, 8 MeV cm2mg−1 and 19 MeV cm2mg−1 respectively. These charges
could also be deposited by single protons as simulated by [116]. It can be seen that the first pulse causes an upset for charges ≥40 fC in the flip flop. Node X is not upset even at 100 fC.
Node X is driven by the output stage of the baker comparator, while the inverter drives X. The inverter is stronger than the output stage and has a larger load capacitance from
VDD_analog OV flag VDD_digital GND Vmod ThMod GND_digital VDD_digital Baker Comparator with filter FF D S R VDD_digital GND_digital GND_digital GND_digital X X Comp out Comparator Logic
Chapter 6 Operation and performance measurements Development of a DCS Chip V [ V ] -0.1 0.7 1.9 V [ V ] -0.1 0.7 1.3 I [u A ] -20.0 140.0 320.0 V [ V ] -0.1 0.7 1.3 V [ V ] -0.1 0.7 1.3 time [ns] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
Figure 6.13: Simulation of an SET in the comparator. Red indicates a pulse of 100 fC, green corresponds to 40 fC and blue to 10 fC. See text for signal description.
the output buffers. Therefore a larger charge is required to upset node X than node X. Even though this simulation is not exhaustive, it shows that a SET in the comparator could set the flags as observed in the data. Furthermore, the voltage pulse created with an injected charge of 100 fC in node X is larger than the tolerance of the technology.
The inverter and buffer used at the comparator output are cells from the standard logic library. Assuming that the upset occurred in these as simulated, the cross-section should be similar as for the registers. Since registers also include buffers and inverters as described in section A.1.2. All seven events for the four comparators used in the PSPPv4 give a cross-section of 5.1 ± 1.9 × 10−14cm2. This is within the uncertainty equal to the
rate measured with the shift register.
Methods to improve the SET tolerance of the comparator can be applied as described in section 3.2. A full triplication of the comparator is probably too intensive in power and area consumption. Adjusting the transistor sizes of the output stage or inserting additional filters would be more suited here.