The following sections will discuss the basics of the different types of memory cells used in modern devices, with the exception of SRAM they are all non-volatile memory technologies, this means that they retain their state when they are not powered. The different technologies have different specifications and offer various benefits to designers, where for example SRAM has the fastest data rate and NAND flash has a greater bit density. The other technologies such as FeRAM, MRAM and Phase Change RAM are being developed as they are non-volatile but have comparable speeds and densities to SRAM. These cells are all contained within standard +3.3 V CMOS devices, where the devices state machine is CMOS based.
SRAM
Typically SRAM devices use a six or four-transistor design, referred to as 6T or 4T SRAM [Baker, 2005], the schematic of the two designs can be seen in Figure 2.7. The 6T design use two nMOS transistors to control the read/write operations and four transistors (two nMOS and two pMOS), in the configuration of two cross coupled inverters, are used for the memory storage cell. For the 4T design, two nMOS transistors are again used to control read/write operations while the two pMOS transistors of the the cross-coupled inverter are omitted and replaced with two high-ohm polysilicon resistors. In most SRAM devices the 6T design is used despite its lower density, this is due to the 4T design being slower, having a higher static current draw and is harder to manufacture with its added polysilicon layer for the high-ohm resistors.
When a logic state of “1” is stored in the 6T cell, the inverter Q holds the state “1”, this is where the pMOS transistor (M4) is ON and the nMOS transistor (M4) is OFF; while the inverter ¯Q holds
the state “0”, where the pMOS transistor (M4) is OFF and the nMOS transistor (M4) is ON. When
the storage cell holds the state “0” then the transistors all have the opposite state. To read the storage cell both bit lines are brought to a threshold voltage between the high and low logic states, the word line (WL) is then brought high turning on both of the access transistors. In the case of the storage cell holding the logic state “1”, then inverter Q pulls the Bit Line (BL) to the logical state “1”, while the inverter ¯Q pulls the ¯BL line to the logical state “0”, the two bit lines, BL and
¯
BL, are both connected to a sense amplifier which then determines if BL > ¯BL or BL < ¯BL i.e. if the storage cell held a “1” or a “0” respectively.
(a) 6T SRAM (b) 4T SRAM
Figure 2.7: Schematic of 6T and 4T SRAM [Inductiveload, 2009]
In order to change a storage cell from a “0” to a “1” the following process is carried out. The BL line is set to the logic high state while ¯BL is set to the logic low state, the word line if then brought high to turn on the access transistors M5 and M6, this causes the cross-coupled inverters to change
state, BL turns M1 ON and M3 OFF, while ¯BL turns M3 OFF and M4 ON, after this the positive
feedback loop keeps the the cell in this state and the word line can be de-asserted thereby isolating the storage cell once more.
Floating Gate Memory
The Floating Gate (FG) transistor, shown in Figure 2.8, is based on the MOS transistor but with a charge storage layer beneath the control gate. The charge storage layer is generally made out of the conductive material polysilicon and is insulated on both sides by silicon dioxide, these insulating layers act as potential barriers allowing charge to remain in the potential well of the FG. The FG is used to store logic states and is achieved by injecting electrons into it or by removing the electrons. When the FG is charged the memory cell is programmed and in the logic state “0”, while when the FG is not charged the cell is Erased and in the “1” state. The presence of this charge in the FG alters the transistor’s threshold voltage, where the programmed state requires a greater voltage to conduct. The state of the cell is determined by biasing the control gate at a reference voltage between the two threshold voltages, if the FG does not hold any charge the transistor will turn on and conduct, while if the FG contains significant charge the FG will remain off. The resultant current draw is then compared to a reference to determine the cells state.
There are two different method of charging the FG, the first, which is used in NOR flash, is called hot-electron injection, the second is called Fowler-Nordheim tunnelling and is used to program NAND flash and erase both NOR and NAND flash. Hot-electron injection involves raising the voltage of the control gate and applying an large voltage to the drain, this creates a lateral field by which some of the electrons flowing between the source and drain gain an energy higher than that required by the Si-SiO2 potential barrier (3.1 eV) and are injected into the FG. Fowler-Nordheim
Figure 2.8: Diagram of a Polysilicon Floating Gate used in Flash [Windbacher, 2010]
Figure 2.9: Diagram Showing the Structure of both NAND and NOR Flash [Micron Technology, 2010]
>10 nm, this process can be used to both program and erase the FG. Fowler-Nordheim tunnelling is a more efficient process than hot-electron injection but it is a much slower process, large currents can however be used to speed the process up [Gerardin et al., 2010].
NOR Flash is a parallel memory which allows for direct random access, it also allows single address write access, however this process is only capable of changing the bits within the address from a “1” to a “0”, if the data write requires a bit to change from a “0” to a “1” then the address needs to be erased. For most NOR devices the erase process occurs on a sector level where multiple addresses, often 64 kB, are erased at the same time. This is due to the high voltage required for this transition [Baker, 2005, Iniewski, 2010].
The differences in the configuration of the FG in NOR and NAND flash can be seen in Figure 2.9. In a NOR device the control gate of the FG transistor is connected to the word line, the source is connected to Ground (GND) and the drain is connected to a bit line.
NAND Flash is a parallel device but requires an internal state machine to access, program or erase an address, read and access is on a page level which normally consists of 2048 bytes with an extra 64 bytes for storage of ECC checksum data, while erase is carried out on the block level (64 pages). As with NOR flash the program operation is only able to convert a logic “1” to a logic “0”, for the opposite the address needs to be erased. The term NAND comes from how the floating gates are arranged, where they are arrange in series between bit line and ground. To read the series of floating gates all but one of the control gates are put to a threshold voltage greater than that needed for a charged (programmed) floating gate transistor to conduct, the remaining floating gate’s control gate is then put at a reference voltage between the erased and programmed state, if the floating gate does not contain significant charge then conduction occurs and the bit line is pulled to ground, however if the floating gate is charged then conduction does not occur and the bit line stays in the logic high state [Iniewski, 2010, Baker, 2005].
Due to the difference in the structure of NAND and NOR flash, at the same fabrication node a NAND cell is also half the size of a NOR flash cell at 4F2 and 10F2 respectively where “F” is the fabrication node. NAND devices which use the FG to store one bit are said to be called textitSingle Level Cells (SLC), while FGs which store more than one bit are called Multi-Level Cells (MLC). MLC devices are much slower than SLC devices and also have a lower reliability, this is due to the required accuracy to separate the four or more voltage thresholds [Gerardin et al., 2010] while programming and reading the FG.
SONOS Technology The non-conducting material Silicon Nitride can also be used as the float- ing gate, this technology is called Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) and the read, write and erase operations are the same as for traditional NOR flash technologies but offers lower pro- gram and erase voltages. As Silicon Nitride is a non-conducting material to store electrons it uses charge trapping sites, this is an added benefit as any damage to the surrounding insulating silicon dioxide does not discharge the whole floating gate, instead only the local charge is lost, this means the device is even more resistant to the wear caused by the program and erase operations [Micheloni et al., 2010]. However there is a new failure route where the electron become permanently attached to the silicon nitride layer, over time, when enough electrons are attached in this way the cell will be unable to revert back to its default logic “1” state [Gerardin et al., 2010].
MirrorBit Technology An expansion of the SONOS technology is to use the material’s non- conductive nature to allow two bits to be stored in a floating gate with the charge located at opposite ends, however this requires more support circuitry and different read, program and erase processes. The read process is based on the fact that the junction depletion region of the drain shields the channel from any charge in the floating gate above the drain, this in turn means that the channel and hence threshold voltage is modulated solely by any charge stored above the source; to read the bit at the other end of the floating gate the source and drain are simply switched. The MirrorBit technology is programmed in the same way as traditional floating gate technology, however as the material is non-conductive the electrons which normally tunnel through the “tunnel oxide” and spread throughout the polysilicon remain in the silicon nitride above the drain, to
Figure 2.10: Diagram of a Silicon Nitride Floating Gate used in MirrorBit Flash [Span- sion, 2004]
Figure 2.11: Diagram showing the Structure of a Fujitsu FeRAM Memory Cell [Fujitsu, 2010]
program the other side the source and drain are again switched. To erase the floating gate, hot carrier injection is used to inject holes into the floating gate and recombine with the electrons, this is done by placing a large positive potential with respect to the control gate on the source, to carry this out on the other side the source and drain are swapped.
FeRAM
FeRAM is based on the one transistor, one capacitor (“1T-1C”) design of Dynamic Random-Access Memory (DRAM) technology, however instead of the dielectric capacitor used in DRAM the fer- roelectric material Lead Zirconate Titanate (PZT) is used. The PZT film is plated on the top and bottom as shown in Figure 2.11, these plates are used to change its state. When the PZT dipole is in a positive polarisation it represents the logic state “0” while when it has a negative polarisation it represents the logic “1” state [Iniewski, 2010, Gerardin and Paccagnella, 2010].
(a) Logic States [Nguyen and Scheick, 2001] (b) Hysteresis Loop [Gerardin et al., 2013]
Figure 2.12: Logic States and Hysteresis Loop of PZT Film
In order to write the logic state “0” to the PZT film the top plate is placed at a positive potential with respect to the bottom plate, this potential is increased moving the PZT crystal along the bottom half of the hysteresis loop shown in Figure 2.12, the potential is then removed from the PZT film and the crystal dipoles stay in the programmed alignment representing the logic state “0”. In order to write a logic state “1” the potential of the two plates either side of the PZT film needs to be inverted, the PZT then follows the top side of the hysteresis loop ending with the dipole having the opposite polarisation.
To read the contents of the PZT film the operation is similar to the write process where by the transistor is used to force the film into a specific state, if the PZT film was in the opposite state, when the dipole inverts, it forces electrons out of one of the plates, in the case of a logic “0” to “1” transition the electrons in the top plate are forced out creating a current pulse, if the film was already in the state applied then no pulse is produced. This means that the read operation is a destructive process which, requires the PZT film to be reprogrammed to its original state.
FeRAM is marketed as an alternative to flash devices with its lower power consumption, faster writes and higher write-erase cycle tolerance, however FeRAM technology densities are not currently comparable to that achieved in NAND flash.
MRAM
Magnetoresistive Random-Access Memory (MRAM) technology is based on the use of ferromagnetic material in a structure called a Magnetic Tunnel Injection (MTJ), where the bottom magnetic field has a fixed magnetic moment while the top layer is free to be programmed parallel or anti-parallel with respect to the bottom layer. In modern MRAM devices a revised technology called Toggle MRAM is used, Figure 2.13 shows the structure of this MTJ where two coupled free ferromagnetic layers are use to store the logic state. Toggle MRAM also has the MTJ placed at 45◦ to the two programming lines, as shown in Figure 2.13, this design then requires the use of a phase shifted pulse in the two write lines to rotate the free ferromagnetic layers the 180◦ needed for it to have
(a) “1T-1MTJ” Toggle MRAM (b) MTJ Structure
Figure 2.13: Structure of a Toggle MRAM Memory Cell and it’s MTJ [Slaughter et al., 2005]
Figure 2.14: Phase Diagram of MRAM Program Operation [Tsiligiannis et al., 2013]
its magnetic moment be parallel and anti-parallel with respect to that of the fixed ferromangetic layer at the base of the MTJ [Tang and Lee, 2010].
To read the state of the MTJ a current is passed through it, if the top magnetic moment is parallel then it has low resistance, while if the top layer is anti-parallel its resistance is higher, by measuring the current at the output it is possible to determine the resistance of the MTJ. Due to the thinness of the insulating material between the two ferromagnetic materials electrons are able to tunnel from one ferromagnet to the other using the tunnel magneto-resistive effect. If the two ferromagnets have the same magnetic moment then tunnelling is more likely to happen than if the two ferromagnets have anti-parallel moments, this is what gives rise to the variable resistance [Iniewski, 2010, Tang and Lee, 2010].
The write operation for Toggle MRAM is shown in Figure 2.14, where H1 is the magnetic field
created by current in the digit line and H2 is the magnetic field created by the current in the bit
line, the operation shown is to rotate the free layer above the tunnel barrier from a parallel to an anti-parallel orientation, which represents a write from logic state “1” to “0”.
Figure 2.15: Diagram showing the Chalcogenide Glass and the Heater below [Micron Technology, 2014]
Phase Change RAM
The PRAM cell is based on a “1T-1C” design, however the transistor in current devices such as the NP8P128A13TSM is a vertical BJT selector. The logic state of the cell is based on the resistance of the chalcogenide layer, where its amorphous state, called “RESET” has a high resistance and its crystalline state, called “SET” has a lower resistance. In order to change the state from “RESET” to “SET” current pulses are applied to the layer in order to heat it above the materials crystallisation temperature, as the material changes to its low resistance state a threshold voltage is meet and the layer is allowed to slowly cool. To change state from “SET” to “RESET” a larger current pulse is applied to the layer melting the material through Joule heating, the material then cools quickly and sets in a high resistance amorphous structure. The heating is carried out by passing a current through a heating element made out of titanium nitride [Kolobov and Tominaga, 2012, Gerardin and Paccagnella, 2010].