Single Event Effects or Single Event Phenomena (SEP) are general terms containing all the re- sponses produced by different semiconductor devices to a single incident ionised particle, including protons, neutrons and heavy ions. This includes both soft errors which be corrected by being rewritten or power cycled and hard errors which cause permanent physical damage to the device. Single Event Upset (SEU) is where a logic cell is changed from a “1” to a “0” or vice-versa by incident ionising radiation. This logic cell can be a memory cell based on one of many technologies e.g. cross-coupled latches (SRAM), a floating gate (NOR/NAND flash), a capacitor (DRAM) or one of the new non-volatile designs (FeRAM, MRAM or PRAM). This upset can be corrected by simply rewriting the correct logic state to the cell. SEU can be used when discussing other devices which use logic cells, the term can also be used in a general fashion for any event which does not fall into any of the following classifications.
Single Bit Upset (SBU) is observed as a single incident ion or particle changing the state of a single memory cell. SBUs are seen in volatile memories such as SRAMs which can be used as stand alone memory devices or used in microprocessors and Field Programmable Gate Arrays (FPGAs). SBUs are also seen in non-volatile memory devices such as NOR/NAND flash, FeRAM, MRAM and PRAM. If all the events observed in a device are SBUs then the cross section represent the total sensitive area of the device.
Multiple Cell Upset (MCU) is where the incident particle creates enough free charge to change the state of at least two memory cells. Newer devices built with processes <130 nm are more susceptible to this type of upset due to the decrease in cell separation. The presence of MCUs will increase the devices cross section and hence the perceived sensitive area.
Multiple Bit Upset (MBU) is where the incident particle is able to change the state of at least two memory cells within the same word. MCUs occur in physical cell neighbours but with the use of interleaving, in most memory devices this means the bits are not in the same word. Only when the MCU is as large or larger than the interleaving scheme implemented does there come a significant chance of two bit upsets being in the same word. However this does have important implications as 2 bit errors in the same word can not be resolved by the most commonly used EDACs. For a memory that does exhibit MBUs a more complex EDAC would be needed with greater storage and processing overheads. MBUs are increasing as a percentage of a device’s SER as technology scales.
Single Event Transients (SET) is where a current or voltage spike is generated by the electron- hole pairs created by the ionising radiation; these transient spikes can propagate through a device physically and temporally, where they may reach the output of the device or cause a SEFI/SEU. SET can affect devices that use combinational or static logic, for example SRAM based FPGAs or the Phase Locked Loop (PLL) circuitry in microcontrollers.
Single Event Functional Interrupt (SEFI) results in the device malfunctioning, this could mean the device resets, locks up or enters a unintended mode of operation, it has also been suggested that a SEFI could be the result of a node within a manufacturer’s electrical functionality test being triggered. SEFIs can occur in memories with internal state machines such as DRAM, NOR/NAND flash or PRAM, it also affects FPGAs, microcontrollers and the other types of processors/control device. To recover from a SEFI the device will need to be reset by software or to be power cycled. During a SEFI event an increase in current consumption is frequently observed, however it is rare that the increase is great enough to cause physical damage, however when this does occur the SEFI is classified as a “Hard” event while the non-destructive event is classified as “Soft” [Bougerol et al., 2010].
Single Event Gate Rupture (SEGR) is the localised dielectric breakdown of the gate oxide and resultant leakage currents under bias. This affects memory devices such as SRAM, DRAM, NOR or NAND flash and is particularly likely while the device is being programmed or erased due
Figure 2.16: Thyristor Structure in CMOS Device, can be Triggered by Charge Pro- duced by Incident Charged Particle [Robinson, 1987]
to the high voltages involved. The process involves an incident ion passing though the isolating oxide creating a high density of electron-hole pairs along its path, if there is large enough potential over this oxide, the capacitor or floating gate will dissipate through the low resistance path left by the incident ion. If a high enough current passes through this track then heating and permanent damage may occur. In DRAM it can be observed as a stuck or oscillating bit if the systems refresh rate is unable to keep the capacitor charged. SEGR is a function of both VGS and LET; VDS is
also a function as it can lower the VGS needed for a SEGR to occur.
Single Event Latchup (SEL) is where incident ionising radiation creates a potentially destruct- ive parasitic thyristor, p-n-p-n, structure, shown in figure 2.16, triggering a low impedance, high current path. This can lead to permanent damage in the bond wires or other parts of the device due to the current consumption of the device increasing above it’s specified maximum operating current. A micro-latchup is where the current increases after an ion strike but is not great enough to melt a bond wire; after the device is power cycled it may still exhibit an increased current con- sumption due to the underlying damage caused to the device. When a device is being power cycled there is a possibility that it may try and source current from connected devices though tier shared pins to try and sustain the thyristor, to avoid this it is recommended that the device is isolated through the use of devices such as optocouplers. For an event to be classed as SEL it needs to be self-sustaining, this is what distinguishes it from events such as “Hard” SEFI.
Single Event Hard Error (SHE) occurs in memory devices, typically SRAMs, where a single bit becomes stuck in a certain state due to permanent or semi-permanent damage caused by ionising radiation [ESCC, 2014]. Stuck bits can not be fixed with a power cycle, however the bit may anneal over time and start to function once more [ESCC, 2014].