The NVAX Cl'! l, the !\.\IC, the NCA, and the back u p cache compose the core o f the system modu le. Th is core architecture was taken directly from the VAX 4000 Model ')()() system. This a rchitecture was cho sen beca use it would meet our performance goals; i t p rovided sim ple i nterfaces to our memo ry, 1/0,
and graph ics su bsystems; and because the design
84
was comp leted and stable. The NVAX CPU is a fu lly custom complementary metal-oxide semicond uc tor (CMOS) CPU fabricated in Digital's 0.75 -micro
meter CMOS-4 process. The N CA and NMC are also fu l ly custom
GvJOS
ch ips, but a re fabricated using D igita l 's l .O-micrometer CMOS-:1 process. The th reecustom chips com m u n icate with each other over a 64-bit bid i rectional bus named the N DA L .
The NVA X C P U con tains a 2KB virtual instruction
cache, an HKB write- through i nstruction/data pri
mary cache, and, on the Model 90, i n terfaces to
a
256KH
write-back instruction/data secondary cache. It contains an on-chip floati ng-pointunit and branch p rediction logic. The NVA)( CPU
pipeli nes instruction execution at the
struction leve l as wel l as the traditiona l micro instruction level .
Table 1 Model 90 Component Sou rce Component
Core chip set Ethernet controller Memory S I M Ms SPXg and SPXgt graphics options TURBOchannel option Synchronous
commun ications option SCSI controller Enclosu re, power supply, cables, brackets Memory transceivers LCSPX graphics option EDAL controller SPXg and SPXgt i nterface Source VAX 4000 Model 500 VAX 4000 Model 500 VAXstation 4000 Model 60 VAXstation 4000 Model 60 VAXstation 4000 Model 60 VAXstation 4000 Model 60 VAXstation 4000 Model 60 VAXstation 4000 Model 60 VAXstation 4000 VLC Modified VXT 2000 mod ule New design New design
The NCA prov ides direct memory access (DMA)
and programmed 1/0 (PIO) support between the 64-bit NDAL bus and two 32-bit bidi rectional COAL
buses named CP 1 and CP2. In the Moclel 90 system, these buses run at an 80-ns cycle time and i n terface to a l l the graphics and 110 devices i n the system. The NCA also contains the VAX standard interval timer register as wel l as many of the l/0 control and status registers.
The NMC services NDAL memory requests using a 64-bit dynamic random-access memory ( DRAM) bus called the NMl, which is p rotected with an error correction code. The NMC, as configured in the Model 90, supports up to 12HM H of m a i n memory. It also supports a directory-based broadcast coher ence p rotocol to maintain coherency between the write-back cache of the NVAX CPU and t he system's DMA devices.
Memory Subsystem
The memory !'iu bsystem of the 1VIodel 90 is based on the design of the V8vV.. 4000 Model ')00 system. In the memory subsyste m , tbe i'\:'viC hand les a l l NDAL memory references by transferring them over tbe 64-bit NMI. The NtviC supports data transfe r rates up
to ')8.5M B per second over the NMI when used with
a 74.4-,VI Iiz NYAX CPU. Memory is configured i n sets; each set contai ns two banks of interleaved 64-bit wide memory. E xtern a l m u ltiplexers and trans ceivers are required to perform interleav i ng. The
Digital Technical }oun1lll V"/. 4 1\'o. 3 Summer 1')')1
The VA Xsta tion 4000 Mode/ 90
N MC provides most of the memory control signals, and only simple bank selection l ogic is required external ly.
The Model 90 memory subsystem implements
two sets of memory using the same :16-hit wide
S I M :'vls that are used i n the Model 60 syste m. Fou r
SIMMs are requ ired for each set. By using either the
4JVIH
or 16MB SIM Ms, the Model 90 al lows memory co nfiguration sizes of 16.VIIl, :)2,VJ B, 64:\<111, HOMB, or12HMB.
Due to module space const raints a nd cost concerns, we i nvestigated a lternatives to the four GMX memory data path chips used on the VAX 4000 Model ')00 memory modu les. We determi ned that two low-cost gate arrays designed for the VAXstation VI.C could he used i nstead . These gate arrays provided the same m ul ti plexer and transceiver fu nctions fou nd i n the c ; :.1 x chips.
Because the N.'vl l on tile Model 90 consists of o n ly two Joacls, the high-drive capabi l ity of the GMX
chips was not requ ired. We used a simpl e PAL to
decode the bank selection signals from tbe NMC and to generate t he control signals requ i red for the gate arrays.
Because the Model 90 design uses the NMC, we received an additional benefi t of hav ing error cor rect io n code protection at no additional cost to the system . The N\1C imp lements a single-bit error cor rect, dou ble-bit error detect code (SEC :/DED) across every 64-bit word of memory data. The eight bits of error correction code replaced the eight bits of par ity used on the Model 60.
1/0 Subsystem
Given that the Model 90 system was an upgrade to the Model 60, a requ irement of the 1/0 subsystem
design was to provide support for a l l I/O devices/options found on the Model 60. The Model 60 1/0 design consisted of an inte rface to a 16-bit
bus known as the EDAL where m ost of t he system 1/0 devices resided. The iVIodel 60 also supported a TlJRROchannel adapter that connected to a ::)2-bit
CDAL bus.
The main task of the Model 90 l/0 subsys
tem design was to provide an interface between the two :)2-bit Cl' buses provided by the i\'CA and the 16-bit EDAL bus and the 32-bit TlJRIIOchannel adapter option offered on the Model 60. The design work necessary i nc luded a sma l l PAL design for the TURROchannel i nterface on the CP2 bus and the design of two programmable gate arravs for the i n terface between the :)2-bit C:P I bus and the 16-bit
NVAX-microprocessor VAX Systems
EDAL. The fol lowing l ist describes the Model 90
I/0 (levices :mel options and explains wlw each
was chosen.
• Ethernet-T'he Model 90 E thernet interface is
implemented with the second-generation E thernet contro ller (SG EC), which provides an
Ethernet connecti o n t h rough a ThinWire or thick-wire cable, selectable by a swi tch on the rear of the system box. The SGEC, \vhich con nects to the CPl bus and was used o n the VAX
4000 Model 500 system, facilitates scatter/gather mapping and dual internal FIFO b u ffering. We chose the VAX 4000 Model ')()() design to i m ple
ment an E thernet control ler because it required no new logic design.
• Sma l l Computer System Interface-The SCSI bus
i n terface is i mplemented using the NCR 5:iC:94 SCSI contro l ler chip that was used on the Model
60. i The NCR 53C94 device connects to t he EDAL
bus and performs DMA operations to and from
main memory i n concert with the two pro grammable gate arrays known as the CEAC and
SQWF DMA v i rtu a l - to-physica l address transla
tion is performed by the SQWF chip based o n
8, 192 mapping registers implemented in exter
n a l static RAMs.
• Serial Lines-The DC708') quad u n iversal asyn chronous receiver/transmit ter (UART) chip was chosen to provide the Model 90 with fou r serial l ines for the keyboard, mouse, modem, and printer/console ports. The DC7085 p rovides a 64-entry FIFO queue that is shared by a l l four receive l ines and is implemented in a small exter nal SRJ\J'vl.
• Sound -The Model 90 sound functionality is
implemented using the A M D 79C:i0 sound chip just as it was in the Model 60. The program med 1/0 interface to this device a l lows both record and playback functions through a jack on the fron t panel, and provides voice-quality sound.
• TURllOcllanneJ -The Model 90 provides a single
s lot i n to which any TURBOchannel option that is supported by the V MS operating system may be instal led . On the Model 60, the TURBOchannel adapter was designed to interface to a CDAL that was not a complete implementation of the gen eral-purpose COAL bus. For the new design, a
small amou nt of interface logic was n ecessary to adapt the Tl lHBOchan nel option to the CP2 bus.
• Synchronous Commu nications Option-The
Model 90 supports the same m u ltiple p rotocol com m u n ications option that is offered by the Model 60. 'l'his i n terface was i mplemented on the EDA L bus ancl a llows use of synchronous wide-area network com m u n ication through pro tOcols such as high- level data l ink control ( H DLC)
and synchronous data l ink control (SDLC) . • Miscel laneous EDAL Devices-The other devices
and registers on the Model 90 16-bit EDAL are a
16-bit system configuration register, an 8-bit light-emitt i ng d iode register, an Ethernet identi fication ll.OJvl , and a \Vatch chip. Al l of these devices also existed on the Model 60 EDAL bus
and were accessed in a similar manner.