1. INTRODUCCIÓN
2.1. CARACTERÍSTICAS DEL PROYECTO
2.1.3. Parámetros de evaluación
The chip layouts for the two Frequency Doubler designs are given in Fig 4.7.
The design fabricated was non-optimum in a number o f ways that significantly degraded performance. Firstly the design was optimised using misleading pulse measurement data. The pulse data was collected at lOps pulses, which is close to one o f the device self heating time constant, giving a misleading measure o f output conductance and hence poor fundamental cancellation. The devices were biased at an operating point that made IC design easy (i.e. \ ^ =0V), but this is not the optimum bias for maximum frequency doubler output (circa V ^ --1.5). The difference between the two operating points is probably a factor o f 3 (lOdB) and this further exasperated the effect o f incomplete fundamental cancellation. It was assumed at the time o f layout that decoupling capacitors could be added external to the chip and that the test instrumentation would not be adversely affected by the lack o f AC coupling. When the measurements were carried out it was not possible to fit decoupling capacitors to the DC probes. The test set produced a DC short circuit, necessitating an emergency AC blocking capacitor arrangement which self resonated in the 60MHz region. The last two difficulties are thought to be the reason that inconsistent and unusable data was produced from the "Voltage Inverter" (Webster) Frequency Doubler.
Despite these difficulties, a number o f key features o f the "Self conductor" (Haigh)
Frequency Doubler were successfully verified. The circuit exhibits broad band
performance covering at least 20-200MHz (The test set could only measure up to 500MHz). A high level o f 3rd harmonic suppression is observed, circa 30dB below the wanted 2nd Harmonic. The 3rd harmonic does not appear to exhibit a rise with frequency in the lOOMHz region supporting the theory that this circuit is much more immune than the "Voltage Inverter" form. The circuit was able to operate over a wide range o f input signal levels. The circuit did exhibit some sensitivity to Vds across each FET suggesting that a correctly optimised version may exhibit some sensitivity to operating voltage.
Pout dBm (Vpj. - 3 V Fin=20MHz) Pout dBm .=3V Pin=6dBm) -10 -20 -30 ^0 -50 -60 -70 -10 0 10 Mn dBm
Pout dBm (Pin OdBm Fin=l(X)MHz)
-20 -30 -40 -50 -60 -70 -80 1 3 5 -10 -20 -30 -40 -50 -60 -70 -80 100 10 1000 fM H z Pout dBm (V5^=4V Pin=6dBm) -20 -25 -35 -40 -45 -50 -55 -60 120 140 100 VpjV(PerFET) fM H z
Fig 4.8 M easu red p erform an ce o f a "self conductor" F r e q u e n c y D o u b ler, (a) P ow er Sw eep , (b) F req u en cy S w eep , (c) S w e ep , (d) F req u en cy Sw eep at op tim u m , O F u n d am en tal , O 2nd and □ 3rd H arm o n ic
4 . 6 S u m m ary
From the above, we conclude the following;-
We have presented an analytical approach that leads to an estimate o f optimum device widths for a resistively loaded 4 FET Linearised Transconductor at medium frequencies based on the Parker Skellem model, providing a good starting point for CAD optimisation.
Prelimary simulations suggest optimum widths are relatively insensitive to statistical variations and bias.
Further work is required in producing an analytical model capable o f accurately predicting optimum widths for 2nd order distortion minimums for higher gains. It is not always possible to null 2nd harmonic distortion in the 4 FET Linearised Transconductor due to a phase reversal in the output stage caused by electrostatic feedback at higher gains.
A similar analysis has been carried out on a Frequency Doubler circuit, showing it is possible to simultaneously null the fundamental and 3rd order distortion.
W e have shown that it is possible to reduce high frequency deterioration in these circuits by using phase matching, phase restoring techniques and alternative circuit topologies.
The use o f intermediate level models is limited for circuit optimisation as they have an incorrect derivative structure. This error is particularly important at higher load resistances where electrostatic feedback is more pronounced.
The apphcation o f Device Circuit Interaction to multi-FET circuits provided an invaluable warning o f which topologies are vulnerable to frequency dependant distortion.
4 . 7 R e fe r e n c e s
1 D.G.Haigh, C.Toumazou, Synthesis of Transconductor / Multiplier Circuits for GaAs Technology, IEEE Trans on CASl Vol. 39, No. 2, Feb1992.
2 D.G.Haigh, A.E.Parker, Compensation of 2nd Harmonic Distortion in a 4 FET Linearised Transconductor Circuit, 1993 ISCAS, Chicago, pp 1089-1092.
3 D.G.Haigh, Circuit Techniques for Efficient Linearised GaAs MMIC's, IEEE International Microwave Symposium, Albuquerque, New Mexico lst-5th June 1992.
4 D.G.Haigh, C.A.Losada, A.E.Parker D.R.Webster, Systematic Approach for the Development and Design of Analogue Communication Circuits, Tutorial 4, 1993 ECCTD, Davos, Switzerland, Aug 30th-Sep 3rd, Ed H Dedieu, Elsevier, Amsterdam
5 C.Toumazou, D.G.Haigh, Design and Application o f GaAs MESFET Current Mirror Circuits, lEE Proc-G, Vol. 137 No. 2, Apr 1990, pplOl-108.
5
Distortion Nullins In the Sinsle Common
Source MESFET
5 . 1 In tr o d u c tio n
In Chapter 2 section 2.6.9-10 we saw that the intermodulation distortion for a common source MESFET amplifier was critically a function o f both its bias and load resistance. In this chapter w e explore the mechanism for distortion nulling with load resistance, showing the importance o f the drain gate mixing terms. W e show how the distortion varies with both load and bias simultaneously with the Parker Skellem MESFET model. W e then compare the Parker Skellem model with the measured behaviour. Finally w e examine the behaviour o f other FET models.
5 , 2 E ffect o f V o lta g e G ain
For a given bias point and medium drive levels (<50mVpk), the 2 port nonlinear transconductance o f the short channel MESFET can be described by a Maclaurin series shown below [1] (Also given in Eqn 2.2.20).
g o +
^ S d s ] y d s ^ S d ^ l ^ d s § d s 3 ^ d s
+ l^ds^gs + 2^ds^gs + ^2 l^ds^gs
Where g i etc. represent the transconductance nonlinearity, gdsi etc. represent the output conductance nonlinearity and the mxy terms represent input output intermodulation associated with the mixed partial derivatives. The series o f (2.1) has been tmncated to include terms up to 3rd order.
W e assume for medium firequencies (lOMHz-lOOMHz), w e can use the extrinsic form o f (5.1) where the effects o f the parasitic source and drain resistances have been absorbed into the transfer characteristic. At medium frequencies, the excitation frequency is above the frequency o f trap and self heating effects, and is sufficiently low that the nonlinear gate
capacitances have no significant effect on the overall distortion. (Later, w e shall present measurements for a 15GHz MESFET in the 20 - 30 MHz region).
For the common source amplifier, w e assume that the gate source voltage Vgg is the input voltage Vin, the drain source v * is the output voltage, and can be related to the input by the voltage gain o f the amplifier Ay.
~ (5*2)
The load resistance Rl is in parallel with the output conductance, hence the effective load resistance is given by
“ ^ l / ( 1 ^L S d sl) (5-3)
Thus the small signal gain can be written as
(5.4)
It is possible to solve iteratively for each o f the nonlinear components present using a Volterra analysis. Here w e describe the harmonic components. Similar equations can be derived for intermodulation products.
v^^(2co) = 0 .5 R ^ f f { g 2 V i n { i c f + g d s 2 ^ d s ( ^ ) ^ } (5.5a)
^ds (3^ ) ~ 0.25 Reff 3 ^in (^ ) 8ds3 ^ds (^ )
+/71i2V^j (w) Vj^(oj )Vj^(w) + ^ 2 1 ( ^ ) Xc/j ( W /%( (^ ) ] (5.5b) +0.5[m i iV^5(2w)V/„((0) + g d s 2 ^ d s ( ^ ^ ) y d s i^ )]}
It is possible to substitute the voltage gain into Eqn 5.5. W e can neglect the contribution o f the 2nd order terms to 3rd order distortion, which generally play a minor role.
v</j(2u) = R e f f h '^ i n ( ^ ) ^ \ S z + « 1 1'^v + S d s Z ^ ) (5.6a)
v * (3 w ) = % v ,« ( u ) ^ i > 3 L 3 + m ,2 A „ + W 2iA ^ + (56b)
It can be seen that the contribution from each distortion term has an amplitude dependant on a single power law o f voltage gain. W e illustrate this by plotting input referred distortion
U t ^ L m v i r [ ) t s ,7 o r r C T o / \ j L t v e L U § ) . ^ 30t -20-- V oL Jf^ & e Q / \ 2 f J Q û 10 15 envelope o f gg and m o i 20-- 10" ICT' -10" -20" -2Œ' -30 5 -15 -10 0 5 10 -10 5 0 5 10 15 c 3 0 T envelope o f gg and mgj' envelope o f gg and m g i 10'■ 10" 83 -10" -20" -20" / ("21 H -30+^--- 1- 1 5 f -15 5 5 15 5 5 -10 0 10 -10 0 10