POR UNA COMUNICACIÓN DESDE LA DISCAPACIDAD

In this thesis, the aim was to reduce power in communication systems, especially in mobile devices. The research started by investigating the types of multi standard digital communication systems. The aim of this investigation was to select the best suited system so as to be the norm of the thesis investigation. The PRFP was the target of this investigation since it used well-defined communication units. Its power consumption was low, and it was adaptable and reconfigurable so that it could work with different communication standards.

The second step after choosing the target communication system was to investigate how power is consumed in digital circuits in order to identify the parameters that affect power consumption in the digital circuits. These parameters can give a better understanding about how to reduce the consumed power in digital circuits.

The third step in this research was to look at the methods of power reduction in digital systems. The aim of this step is to select a method that can be used in the multi standard digital communication system. DVFS was chosen due to its ability to reduce the overall consumed power of the digital circuit by reducing the supply voltage. Another feature that makes this method the best choice among power reduction methods is its ease of implementation and control. Its only limitation in communication system is that it uses the task time as a governing parameter and that does not exist in communication circuits. This limitation was overcome by using the clock frequency of the system as the controlling parameter to this method.

From the energy equation of the CMOS circuits, a proposed model for power consumption in digital circuit was derived. This model includes the load capacitor of the gates, the effect of input changes on the gates, and connectivity of the gates. These parameters were not accounted for in the previous power models. To verify the integrity of the model, it was implemented using MATLAB to measure the power consumption of the NOT gate, 2×1 MUX, 1-bit FA, and 2-bit FA circuits. These are the most used circuits in digital systems. The results of the new power model were compared with an implementation to the same circuits using OrCAD Cadence. The simulation showed that the new power model can simulate the dynamic power consumption of the digital circuit efficiently. Furthermore, the new model can work with large digital systems which is a privilege OrCAD Cadence cannot provide.

In many SDR and multi-standard communication systems, clock frequency changes to cope with the changing requirements of the system. This feature is used in this research to build SPM. SPM is a smart unit that can make use of the frequency changes to manipulate the

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supply voltage of the system so that it reduces the dynamic consumed power. SPM uses the clock frequency and the measured power as its input, and produces Vdd as the output. The core

of the SPM is an FLC that has rules designed specially to reduce power without affecting the time delay of the logic circuit.

SPM was tested using 2×1 MUX, and 2-bit FA circuits. The test took place using different frequencies ranging from few MHz to GHz. The reason for this range is that for SDR the targeted operating frequency is very high. The high frequency range was chosen to prove the ability of SPM to fit in SDR. To deal with such a kind of range, a log scaling technique was used so as to map the frequencies and measured power into the corresponding fuzzy universe of discourse.

The results of the simulation showed that SPM can reduce power in all frequency ranges. It is most powerful in the low frequency ranges but it can reduce no less than 10% of the consumed power in very high frequencies.

The first stage of the Tang architecture was the CRC stage. This stage was explored to produce parallel circuits capable of producing the 8, 16, and 24 bit CRC remainder. These circuits are the norm of the LTE standard. To reduce the number of gates, the size, and hence the power of such circuits, a new multi-polynomial circuit was designed. This circuit combined the three CRC circuits into one general circuit that has a fewer number of gates and size. The multi-polynomial circuit can work under the LTE standard and produce the required remainder by selecting it using three selection lines.

The 8, 16, and 24 bit CRC circuits were used as a test bench for the SPM to prove the SPM ability to reduce the power in digital communication systems. The same frequency range was used in this test. The SPM proved its ability to control the consumed power efficiently even in very high frequency.

The SPM unit was tested using many circuits. Some of these circuits were very small in size and some were large. The circuits had different architectures, and number of inputs. In all the situations, SPM was able to reduce the circuit’s power using only the power readings and the clock frequency of the system.

The final step in this research was to implement SPM in an LTE system. The system clock setting was discussed to find the point in which the system clock frequency needs to change. The point was when changing between CRC circuits and the type of modulation. This point happened because the system needed a constant throughput at the output. SPM uses these

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changes to efficiently reduce the consumed power in the CRC stage especially when a 24 bit CRC was used with the QPSK modulation.