(single-stepped): T flag = 1
ISR for INT 1; Part of Debug Monitor. T flag = 0
Software Interrupt Instructions (INT n):
These instructions appear as regular instructions in the program code.
• INT 3 is 1 –Byte long. (The only special case). Rest of INT n instructions are all 2 – Byte long.
• These instructions are commonly used to access system procedures. Example: INT 21H to access DOS services.
• A software interrupt instruction is more convenient than far call. It occupies less memory as it needs only 1 or 2 bytes as against the 5 bytes required for a far Call. Further, there is no need to remember the CS:IP values. These values are obtained from the Interrupt Vector Table.
INT 3 Instruction:
• Only INT n instruction that is 1 Byte long! Rest are 2 – Byte long.
• This is often used to effect a “breakpoint” in the program. The breakpoint service routine can provide Register values and other information useful for debugging. Any INT n can be used for implement a breakpoint. However, as INT 3 is only 1-byte long, it is comparatively easier to insert this instruction into the program.
INTO Instruction:
• This instruction causes an Interrupt on Overflow. Thus if the O flag = 1, an interrupt is generated as Interrupt Vector 4. And if the O flag = 0 , this instruction results in no operation.
• This instruction is placed in the program usually after arithmetic instructions that may lead to overflow condition. (Recall that JO instruction also detects overflow condition.)
Interrupts in PC:
• Type codes 0 to 4 are used in the standard way.
• Several interrupt type codes are dedicated to interrupts from hardware devices like key board, mouse etc. Examples: 9 for Keyboard; 17H for Parallel Port.
• Software interrupt instructions commonly used in Assembly Language Programs are: – INT 21H : DOS Services
– INT 27H : Terminate and Stay Resident (TSR) – INT 1AH : Clock Service etc.
Unit - 5
8086
INTERFACING
Keyboard Interface of 8279
1. The keyboard matrix can be any size from 2x2 to 8x8.
2. Pins SL2-SL0 sequentially scan each column through a counting operation. 3. The 74LS138 drives 0’s on one line at a time.
4. The 8279 scans RL pins synchronously with the scan.
5. RL pins incorporate internal pull-ups, no need for external resistor pullups. 6. Unlike the 82C55, the 8279 must be programmed first.
The first 3 bits of # sent to control port selects one of 8 control words. First three bits given below select one of 8 control registers (opcode). 000DDMMM
Mode set: Opcode 000. DD sets displays mode. MMM sets keyboard mode. DD field selects either:
8- or 16-digit display
Whether new data are entered to the rightmost or leftmost display position.
MMM field:
Encoded: Sl outputs are active-high, follow binary bit pattern 0-7 or 0-15.
Decoded: SL outputs are active-low (only one low at any time). Pattern output: 1110, 1101, 1011, 0111.
Strobed: An active high pulse on the CN/ST input pin strobes data from the RL pins into an internal FIFO for reading by micro later.
2-key lockout/N-key rollover: Prevents 2 keys from being recognized if pressed simultaneously/Accepts all keys pressed from 1st to last.
Interface of 8279 001PPPPP
The clock command word programs the internal clock driver.
The code PPPPP divides the clock input pin (CLK) to achieve the desired operating frequency, e.g. 100KHz requires 01010 for a 1 MHz CLK input.
010Z0AAA
The read FIFO control word selects the address (AAA) of a keystroke from the FIFO buffer (000 to 111).
Z selects auto-increment for the address. 011ZAAAA
The display read control word selects the read address of one of the display RAM positions for reading through the data port.
100ZAAAA
Selects write address -- Z selects auto-increment so subsequent writes go to subsequent display positions.
1010WWBB
The display write inhibit control word inhibits writing to either the leftmost 4 bits of the display (left W) or rightmost 4 bits.
BB works similarly except that they blank (turn off) half of the output pins. 1100CCFA
The clear control word clears the display, FIFO or both Bit F clears FIFO and the display RAM status, and sets address pointer to 000.
If CC are 00 or 01, all display RAM locations become 00000000. If CC is 10, --> 00100000, if CC is 11, --> 11111111.
1110E000
End of Interrupt control word is issued to clear IRQ pin in sensor matrix mode.
1) Clock must be programmed fi rst. If 3.0 MHz drives CLK input, PPPPP is programmed to 30 or 11110.
2) Keyboard type is programmed next. The previous example illustrates an encoded keyboard, external decoder used to drive matrix.
3) Program the FIFO.
Once done, a procedure is needed to read data from the keyboard.
To determine if a character has been typed, the FIFO status register is checked.
When this control port is addressed by the IN instruction, the contents of the FIFO status word is copied into register AL:
Code given in text for reading keyboard.
Row and column number are given the rightmost 6 bits (scan/return).
This can be converted to ASCII using the XLAT instruction with an ASCII code lookup table. The CT and SH indicate whether the control or shift keys were pressed.
The Strobed Keyboard code is just the state of the RLx bits at the time a 1 was ‘strobed’ on the strobe input pin.
Basic I/O Instructions
We discussed IN, OUT, INS and OUTS as instructions for the transfer of data to and from an I/O device. IN and OUT transfer data between an I/O device and the microprocessor’s
accumulator (AL, AX or EAX). The I/O address is stored in:
• Register DX as a 16-bit I/O address (variable addressing). • The byte, p8, immediately following the opcode (fixed address).
Only 16-bits (A0 to A15) are decoded.
Address connections above A15 are undefined for I/O instructions. 0000H-03XXH are used for the ISA bus. INS and OUTS transfer to I/O devices using ES:DI and DS:SI, respectively.
Isolated versus Memory-Mapped I/O Isolated and Memory-Mapped I/O:
In the Isolated scheme, IN, OUT, INS and OUTS are required.
8-bit port addresses used to access system board device, e.g. timer and keyboard. 16-bit port addresses used to access serial and parallel ports, harddrives, etc. I/O Map
The basic input device (to the microprocessor) is a set of tri-state buffers. The basic output device (from the microprocessor) is a set of latches.
Handshaking
a. I/O devices are typically slower than the microprocessor.
b. Handshaking is used to synchronize I/O with the microprocessor.
c. A device indicates that it is ready for a command or data (through some I/O pin or port). d. The processor issues a command to the device, and the device indicates it is busy (not
ready).
e. The I/O device fi nishes its task and indicates a ready condition, and the cycle continues. f. There are two basic mechanisms for the processor to service a device.
g. Polling: Processor initiated. Device indicates it is ready by setting some status bit and the processor periodically checks it.
h. Interrupts: Device initiated. The act of setting a status bit causes an interrupt, and the processor calls an ISR to service the device.
Programmable Peripheral Interface (82C55)
a. The 82C55 is a popular interfacing component, that can interface any TTLcompatible I/O device to the microprocessor.
b. It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated chipset).
c. Requires insertion of wait states if used with a microprocessor using higher that an 8 MHz clock.
d. PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct modes of operation.
82C55: Mode 0 Operation
Mode 0 operation causes the 82C55 to function as a buffered input device or as a latched output device.
In previous example, both ports A and B are programmed as (mode 0) simple latched output ports.Port A provides the segment data inputs to display and port B provides a means of selecting one display position at a time. The values for the resistors and the type of transistors used are determined using the current requirements (see text for details). Textbook has the assembly code fragment demonstrating its use.
82C55: Mode 1 Strobed Input
Port A and/or port B function as latching input devices. External data is stored in the ports until the microprocessor is ready. Port C used for control or handshaking signals (cannot be used for data). Signal definitions for Mode 1 Strobed Input
INTR Interrupt request is an output that requests an interrupt
IFB Input buffer full is an output indicating that the input latch contain information STB The strobe input loads data into the port latch on a 0-to-1 transition
INTE The interrupt enable signal is neither an input nor an output; it is an internal bit programmed via the PC4(port A) or PC2(port B) bits.
PC7,PC6 The port C pins 7 and 6 are general-purpose I/O pins that are available for any purpose.
Keyboard encoder debounces the key-switches, and provides a strobe whenever a key is depressed.
DAV is activated on a key press strobing the ASCII-coded key code into Port A.
82C55: Mode 1 Strobed Output
Similar to Mode 0 output operation, except that handshaking signals are provided using port C. Signal Definitions for Mode 1 Strobed Output
OBF Output buffer full is an output that goes low when data is latched in either port A or port B. Goes low on ACK.
ACK The acknowledge signal causes the OBF pin to return to 0. This is a response from an external device.
INTR Interrupt request is an output that requests an interrupt
INTE The interrupt enable signal is neither an input nor an output; it is an internal bit programmed via the PC6(port A) or PC2(port B) bits.
PC5,PC4 The port C pins 5 and 4 are general-purpose I/O pins that are available for any purpose.
82C55: Mode 2 Bi-directional Operation
Only allowed with port A. Bi-directional bused data used for interfacing two computers, GPIB interface etc.
INTR Interrupt request is an output that requests an interrupt
OBF Output buffer full is an output indicating that the output buffer contains data for the bi- directional bus
ACK Acknowledge is an input that enables tri-state buffers which are otherwise in their high- impedance state
STB The strobe input loads data into the port A latch
IFB Input buffer full is an output indicating that the input latch contains information for the external bi-directional bus
INTE Interrupt enable are internal bits that enable the INTR pin. Bit PC6(INTE1) and PC4(INTE2)
PC2,PC1 and PC0 Theses port C pins are general-purpose I/O pins that are available for any purpose.
82C55: Mode 2 Bi-directional Operation
Timing diagram is a combination of the Mode1 Strobed Input and Mode 1 Strobed Output Timing diagrams.