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PRSNT[1::2]# in The Present signals are not signals for a device, but are provided by an add-in card. The Present signals indicate to the system board whether an add-in card is physically present in the slot and, if one is present, the total power requirements of the add-in card. These signals are required for add-in cards but are optional for system boards. Refer to Section 4.4.1. for more details.

IMPLEMENTATION NOTE

PRSNT# Pins

At a minimum, the add-in card must ground one of the two PRSNT[1::2]# pins to indicate to the system board that an add-in card is physically in the connector. The signal level of PRSNT1# and PRSNT2# inform the system board of the power requirements of the add-in card. The add-in card may simply tie PRSNT1# and/or PRSNT2# to ground to signal the appropriate power requirements of the add-in card. (Refer to Section 4.4.1 for details.) The system board provides pull-ups on these signals to indicate when no add-in card is currently present.

CLKRUN# in, o/d, s/t/s

Clock running is an optional signal used as an input for a device to determine the status of CLK and an open drain output used by the device to request starting or speeding up ^CLK.

CLKRUN# is a sustained tri-state signal used by the central resource to request permission to stop or slow CLK. The central resource is responsible for maintaining CLKRUN# in the asserted state when ^CLK is running and deasserts ^CLKRUN#to request permission to stop or slow ^CLK. The central resource must provide the pullup for CLKRUN#.

IMPLEMENTATION NOTE

CLKRUN#

CLKRUN# is an optional signal used in the PCI mobile environment and not defined for the connector. Details of the CLKRUN# protocol and other mobile design considerations are discussed in the PCI Mobile Design Guide.

M66EN in The 66MHZ_ENABLE pin indicates to a device whether the bus segment is operating at 66 or 33 MHz. Refer to

Section 7.5.1 for details of this signal's operation.

PME# o/d The Power Management Event signal is an optional signal that can be used by a device to request a change in the device or system power state. The assertion and deassertion of PME# is

asynchronous to CLK. This signal has additional electrical requirements over and above standard open drain signals that allow it to be shared between devices which are powered off and those which are powered on. In general, this signal is bused between all PCI connectors in a system, although certain implementations may choose to pass separate buffered copies of the signal to the system logic.

Devices must be enabled by software before asserting this signal. Once asserted, the device must continue to drive the signal low until software explicitly clears the condition in the device.

The use of this pin is specified in the PCI Bus Power Management Interface Specification. The system vendor must provide a pull-up on this signal, if it allows the signal to be used. System vendors that do not use this signal are not required to bus it between connectors or provide pull-ups on those pins.

3.3Vaux in An optional 3.3 volt auxiliary power source delivers power to the PCI add-in card for generation of power management events when the main power to the card has been turned off by software.

The use of this pin is specified in the PCI Bus Power Management Interface Specification.

A system or add-in card that does not support PCI bus power management must treat the 3.3Vaux pin as reserved.

IMPLEMENTATION NOTE

PME# and 3.3Vaux

PME#and 3.3Vaux are optional signals defined by the PCI Bus Power Management Interface Specification. Details of these signals can be found in that document.

2.2.8. 64-Bit Bus Extension Pins (Optional)

The 64-bit extension pins are collectively optional. That is, if the 64-bit extension is used, all the pins in this section are required.

AD[63::32] t/s Address and Data are multiplexed on the same pins and provide 32 additional bits. During an address phase (when using the DAC command and when REQ64# is asserted), the upper 32-bits of a 64-bit address are transferred; otherwise, these bits are reserved⁷ but are stable and indeterminate. During a data phase, an additional 32-bits of data are transferred when a 64-bit transaction has been negotiated by the assertion of REQ64# and ACK64#.

C/BE[7::4]# t/s Bus Command and Byte Enables are multiplexed on the same pins.

During an address phase (when using the DAC command and when REQ64# is asserted), the actual bus command is transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate.

During a data phase, C/BE[7::4]# are Byte Enables indicating which byte lanes carry meaningful data when a 64-bit transaction has been negotiated by the assertion of REQ64# and ACK64#. C/BE[4]#

applies to byte 4 and C/BE[7]# applies to byte 7.

REQ64# s/t/s Request 64-bit Transfer, when asserted by the current bus master, indicates it desires to transfer data using 64 bits. ^REQ64# also has the same timing as FRAME#. REQ64# also has meaning at the end of reset as described in Section 3.8.1.

ACK64# s/t/s Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64 bits. ACK64#

has the same timing as DEVSEL#.

7Reserved means reserved for future use by the PCI SIG Board of Directors. Reserved bits must not be used by any device.

PAR64 t/s Parity Upper DWORD is the even⁸ parity bit that protects AD[63::32]

and C/BE[7::4]#. ^PAR64 must be valid one clock after each address phase on any transaction in which ^REQ64# is asserted.

PAR64 is stable and valid for 64-bit data phases one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. (^PAR64 has the same timing as ^AD[63::32]

but delayed by one clock.) The master drives ^PAR64 for address and write data phases; the target drives PAR64 for read data phases.