STUDIES THROUGH 2018

A bridge must adhere to the latency requirements of the PCI Local Bus Specification. These requirements include the following:

• Target Initial Latency

• Target Subsequent Latency

• Master Data Latency

• Memory Write Maximum Completion Time (for internal bridge registers)

• Master Latency Timer Timeout

When the bridge is responding as a target to a transaction, it must complete the initial data phase within 16 clocks (Target Initial Latency) and terminate subsequent data phases (of the same transaction) within eight clocks (Target Subsequent Latency). To comply with these target latency requirements, a bridge must use Delayed Transactions to complete non-posted transactions that cross the bridge.

7 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win arbitration at a given instant in time.

Master Data Latency is the number of clocks the master takes to assert IRDY# indicating it is ready to complete the data phase and transfer data. All PCI devices including bridges are required to assert IRDY# within eight clocks of the assertion of FRAME# on the initial data phase and within eight clocks on all subsequent data phases.

The PCI Local Bus Specification requires targets to complete at least one data phase of a Memory Write or Memory Write and Invalidate transaction within a specified number of PCI clocks (Maximum Completion Time) but grants an exception to bridges when the transaction crosses a bridge. However, a bridge must adhere to the Maximum Completion Time (334 clocks at 33 MHz or slower and 668 clocks at 66 MHz) when a Memory Write or Memory Write and Invalidate transaction accesses a location within (or associated with) the bridge. The Maximum Completion Time requirement is not in effect during device initialization time, which is defined as the 2²⁵ PCI clocks immediately following the deassertion of RST#.

The Master Latency Timer limits the tenure of a PCI bus master when it is using the bus. When the bridge is a master on the primary interface, it must relinquish the bus when its primary interface GNT# has been deasserted and the Master Latency Timer expires. When the bridge is a master on the secondary interface, it must relinquish the bus when its secondary interface GNT#⁸ has been deasserted and the Secondary Master Latency Timer expires. When the Master Latency Timer expires and GNT# is deasserted while the bridge is the master of a Memory Write and Invalidate transaction, it must ignore the timeout condition until a cacheline boundary is reached (see the PCI Local Bus Specification for more details).

8 When the bridge provides an arbiter for the secondary bus, this grant may be an internal signal.



Chapter 9 Interrupt Support

9.1. Interrupt Routing

A bridge is not required to route interrupts that originate on the PCI bus connected to the secondary interface of the bridge through the bridge. The PCI Local Bus Specification requires the interrupt handler (service routine), or the device which originates the interrupt, to guarantee that all buffers are flushed between the device and the final destination. This can be

accomplished by the interrupt service routine of the device driver by performing a read of the device or by the device itself performing a read of the location last written by the device. In either case, the read will force buffers between the device and the final destination to be flushed.

No special buffer flushing requirements exist for devices that use Message Signaled Interrupts, as defined by the PCI Local Bus Specification. Interrupt messages naturally flush buffers.

However, since bridges will be used on expansion boards, the BIOS will assume an association between device location and which INTx# line it uses when requesting an interrupt. Since only the BIOS knows how PCI INTx# lines are routed to the system interrupt controller, a mechanism is required to inform the device driver which IRQ its device will request an interrupt on. The Interrupt Line register (see Section 3.2.5.15.) is used to store this information. The BIOS code will assume the following binding behind the bridge and will write the IRQ number in each device as described in Table 9-1. The interrupt binding defined in this table is mandatory for expansion boards utilizing a bridge.

Table 9-1: Interrupt Binding for Devices Behind a Bridge Device Number

on Add-in Bus

Interrupt Pin on Device

Interrupt Pin on Connector

INTA# INTA#

0, 4, 8, 12, INTB# INTB#

16, 20, 24, 28 INTC# INTC#

INTD# INTD#

INTA# INTB#

1, 5, 9, 13, INTB# INTC#

17, 21, 25, 29 INTC# INTD#

INTD# INTA#

INTA# INTC#

2, 6, 10, 14, INTB# INTD#

18, 22, 26, 30 INTC# INTA#

INTD# INTB#

INTA# INTD#

3, 7, 11, 15, INTB# INTA#

19, 23, 27, 31 INTC# INTB#

INTD# INTC#

Device 0 on a secondary bus will have its INTA# line connected to the INTA# line of the connector. Device 1 will have its INTA# line connected to INTB# of the connector. This sequence continues and then wraps around once INTD# has been assigned.

When POST code is initializing the system, it assumes the previous routing information for devices on an expansion board that utilizes a bridge. POST code writes the appropriate IRQ information in each device’s Interrupt Line register.

Note that Table 9-1 does not specify the routing of a bridge’s interrupt pin (if implemented) to the interrupt pins of the add-in connector. Assuming that the bridge is a single function device, its interrupt pin is required to be connected to INTA# by the PCI Local Bus Specification.



Chapter 10 Signal Pins

10.1. Primary PCI Interface

10.1.1. Required Signals

The primary bus requires 50 signals to support PCI. These signals are listed below according to signal type.

Signal type:

s/t/s FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, PERR#

t/s AD[31::00], PAR, C/BE[3::0]#, REQ#

Input IDSEL, CLK, RST#, GNT#, LOCK#⁹ o/d SERR#

10.1.2. Optional Signals

The primary interface of the bridge may optionally support the 64-bit extensions, Power Management, JTAG, and 66 MHz operation to provide more functionality or performance as needed. The bridge may also provide an interrupt pin, if necessary, to support implementation-specific functions.

Signal type:

s/t/s REQ64#, ACK64#

t/s AD[63::32], PAR64, C/BE[7::4]#

Input TDI, TCK, TMS, TRST#, M66EN¹⁰

9 Note that in the prior version of the PCI-to-PCI Bridge Architecture Specification LOCK# was defined as a s/t/s on the primary interface. However, the PCI Local Bus Specification constrains the use of LOCK# to downstream transactions.

Output TDO

o/d INTA#, PME#

other 3.3 Vaux