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REGISTER FRAMER

ADDRESSES FUNCTION

Transmit DS0 Channel Monitor Select

(TDS0SEL) 189h Transmit channel to be monitored.

Transmit DS0 Monitor Register

(TDS0M) 1BBh Monitored data.

Receive Channel Monitor Select Register

(RDS0SEL) 012h Receive channel to be monitored.

Receive DS0 Monitor Register

(RDS0M) 060h Monitored data.

In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM[4:0] bits in the TDS0SEL register. In the receive direction, the RCM[4:0] bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM[4:0] bits appear in the Transmit DS0 Monitor register (TDS0M) and the DS0 channel pointed to by the RCM[4:0] bits appear in the Receive DS0 Monitor register (RDS0M). The TCM[4:0] and RCM[4:0] bits should be programmed with the decimal decode of the appropriate T1 or E1 channel.

T1 channels 1 to 24 map to register values 0 to 23. E1 channels 1 to 32 map to register values 0 to 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL:

TCM4 = 0 RCM4 = 0 TCM3 = 0 RCM3 = 1 TCM2 = 1 RCM2 = 1 TCM1 = 0 RCM1 = 1 TCM0 = 1 RCM0 = 0

8.9.11 Transmit Per-Channel Idle Code Insertion

Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions.

The Transmit Idle Code Definition registers (TIDR1:TIDR32) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1:TCICE4) are used to enable idle code replacement on a per-channel basis.

8.9.12 Receive Per-Channel Idle Code Insertion

Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Receive Idle Code Definition registers (RIDR1:RIDR32) are provided to set the 8-bit idle code for each channel.

The Receive Channel Idle Code Enable registers (RCICE1:RCICE4) are used to enable idle code replacement on a per-channel basis.

8.9.13 Per-Channel Loopback

The Per-Channel Loopback Enable registers (PCL1:PCL4) determine which channels (if any) from the backplane should be replaced with the data from the receive side, i.e., off the T1 or E1 line. If this loopback is enabled, the transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back.

Each of the bit positions in the Per-Channel Loopback Enable registers (PCL1:PCL4) represents a DS0 channel in the outgoing frame. When these bits are set to 1, data from the corresponding receive channel replaces the data on TSER for that channel.

8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)

The DS26521 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa-bit positions and this change in data content will be used to modify the CRC-4 checksum. This modification, however, does not corrupt any error information the original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode.

The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input, the user must assert TSYNC aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe align the data presented to TSER. This mode is enabled with the TCR3.0 control bit (CRC4R). Note that the E1 transmitter must already be enabled for CRC insertion with the TCR1.0 control bit (TCRC4).

Figure 8-14. CRC-4 Recalculate Method

TSER

8.9.15 T1 Programmable In-Band Loop Code Generator

The DS26521 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode.

Table 8-25. Registers Related to T1 In-Band Loop Code Generator

REGISTER FRAMER

ADDRESSES FUNCTION

Transmit Code Definition Register 1

(T1TCD1) 1ACh Pattern to be sent for loop code.

Transmit Code Definition Register 2

(T1TCD2) 1ADh Length of the pattern to be sent.

Transmit Control Register 3 (TCR3) 183h TLOOP bit for control of number of patterns being sent.

Transmit Control Register 4 (TCR4) 186h Length of the code being sent.

To transmit a pattern, the user loads the pattern to be sent into the Transmit Code Definition registers (T1TCD1 and T1TCD2) and selects the proper length of the pattern by setting the TC1 and TC0 bits in Transmit Control Register 4 (TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern, both T1TCD1 and T1TCD2 must be filled with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires T1TCD1 to be filled. Once this is accomplished, the pattern is transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer overwrites the repeating pattern once every 193 bits to allow the F-bit position to be sent.

As an example, to transmit the standard loop-up code for Channel Service Units (CSUs), which is a repeating pattern of ...10000100001..., set TCD1 = 80h, TC0 = 0, TC1 = 0, and TCR3.0 = 1.

8.9.16 T1 Programmable In-Band Loop Code Detection

The DS26521 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode.

Table 8-26. Registers Related to T1 In-Band Loop Code Detection

REGISTER FRAMER

ADDRESSES FUNCTION

Receive In-Band Code Control Register

(T1RIBCC) 082h Used for selecting length of receive in-band loop code register.

Receive Up Code Definition Register 1

(T1RUPCD1) 0ACh Receive up code definition register 1.

Receive Up Code Definition Register 2

(T1RUPCD2) 0ADh Receive up code definition register 2.

Receive Down Code Definition Register 1

(T1RDNCD1) 0AEh Receive down code definition register 1.

Receive Down Code Definition Register 2

(T1RDNCD2) 0AFh Receive up code definition register 2.

Receive Spare Code Register 1 (T1RSCD1) 09Ch Receive spare code register 1.

Receive Spare Code Register 2 (T1RSCD2) 09Dh Receive spare code register 2.

Receive Real-Time Status Register 3 (RRTS3) 0B2h Real-time loop code detect.

Receive Latched Status Register 3 (RLS3) 092h Latched loop code detect bits.

Receive Interrupt Mask Register 3 (RIM3) 0A2h Mask for latched loop code detect bits.

The framer has three programmable pattern detectors. Typically, two of the detectors are used for “loop-up” and

“loop-down” code detection. The user programs the codes to be detected in the Receive Up Code Definition registers (T1RUPCD1 and T1RUPCD2) and the Receive Down Code Definition registers (T1RDNCD1 and T1RDNCD2). The length of each pattern is selected via the Receive In-Band Code Control register (T1RIBCC).

There is a third detector (Spare) and it is defined and controlled via the T1RSCD1/T1RSCD2 and T1RSCC registers. When detecting a 16-bit pattern, both receive code definition registers are used together to form a 16-bit register. For 8-bit patterns, both receive code definition registers are filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer detects repeating pattern codes in both framed and unframed circumstances with bit-error rates as high as 10E-2.

The detectors can handle both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the receive code definition register resets the integration period for that detector. The code detector has a nominal integration period of 48ms. Thus, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and LSP) is set to 1. Note that real-time status bits, as well as latched set and clear bits, are available for LUP, LDN, and LSP (RRTS3 and RLS3). Normally codes are sent for a period of 5 seconds. It is recommended that the software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously present.

8.9.17 Framer Payload Loopbacks

The framer, payload, and remote loopbacks are controlled by Receive Control Register 3 (RCR3).