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Although any synchronous sequential system can be designed in terms of one or more state machines, in practice this is likely to result in the ‘reinvention of the wheel’ on many occasions. For example, the right-hand state machine of Figure 7.3 is simply an 8-bit counter. Given this, it is obviously more effective to reuse an existing counter, either as a piece of hardware or as a VHDL model. It is therefore convenient to think of a sequential system in terms of the datapath, i.e. those components that have been pre-viously designed (or that can be easily adapted) and that can be reused, and the controller, which is a design-specific state machine. A model of a system partitioned in this way is shown in Figure 7.6.

Returning to the example of Figure 7.3, it can be seen that the left-hand state machine corresponds to a controller, while the right-hand state machine, the counter, corresponds to the datapath. The TIMED signal is a status signal, as shown in Figure 7.6, while the ENABLE signal is a control signal. We will look at a more significant example of datapath/controller partitioning in Section 7.4.

The datapath would normally contain registers. As the functionality of the system is mainly contained in the datapath, the system can be described in terms of register transfer operations. These register transfer operations can be described using an exten-sion of ASM chart notation. In the simplest case a registered output can be indicated as shown in Figure 7.7(a). This notation means that Z takes the value 1 at the end of the state indicated, and holds that value until it is reset. If, in this example, Z is reset to 0, and it is set to 1 only in the state shown, the registered output would be imple-mented as a flip-flop and multiplexer, as shown in Figure 7.7(b), or simply as an enabled flip-flop as shown in Figure 7.7(c). In either implementation, the ENABLE signal is asserted only when the ASM is in the indicated state. Thus the ASM chart could equally include the ENABLE signal, as shown in Figure 7.7(d).

A more complex example is shown in Figure 7.8. In state 00, three registers, B0, B1

and B2, are loaded with inputs X0, X1 and X2, respectively. Input A then determines whether a shift left, or multiply by 2, is performed (A 0) or a shift right, or divide by 2 (A  1) in the next state. If a divide by 2 is performed, the value of the least

Datapath/controller partitioning 161

Figure 7.7 Extended ASM chart notation.

ENABLE (d)

Z 1

(a) (b)

(c) ENABLE

ENABLE

1 2D Z

G1 C2 1 1

G1

C2

1 2D Z

Figure 7.8 ASM chart of partitioned design.

B0 X0

B1 X1

B2 X2

00

0 1

1 0

11 01 10

B0 0 B1 B0

B2 B2

B0 B0 B1

B1 B1 B2

B2 B2.B1.B0

B0 B1

B1 B2

B2 0 A

X₀

significant bit is tested, so as always to round up. From the ASM chart we can derive next state equations for the controller, either formally or by inspection:

The datapath part of the design can be implemented using registers for B0, B1and B2

and multiplexers, controlled by S0and S1, to select the inputs to the registers, as shown in Figure 7.9. It is also possible to implement the input logic using standard gates and thus to simplify the logic slightly.

S1 S⁰.S1.A S0 S⁰.S1.1A  X⁰2

162 Complex sequential systems

Figure 7.9 Implementation of datapath.

S1 S0

1In fact, most compilers would compile directly to machine code. For the purposes of this discussion, it is easier to think in terms of assembler instructions.

7.3 Instructions

Before looking at how a very simple microprocessor can be constructed, we will exam-ine the interface between hardware and software. This is not a book on computer archi-tecture – many such books exist – so the concepts presented here are deliberately simplified.

When a computer program written in, say, C is compiled, the complex expressions of the high-level language can be broken down into a sequence of simple assembler instructions. These assembler instructions can then be directly translated into machine code instructions.¹These machine code instructions are sets of, say, 8, 16 or 32 bits. It is the interpretation of these bits that is of interest here.

Let us compile the expression a = b + c;

to a sequence of assembly code instructions:

LOAD b ADD c STORE a

A simple microprocessor 163

The exact interpretation of these assembler instructions will be explained in the next section. If the microprocessor has eight bits, the opcode (LOAD, STORE, etc.) might require three bits, while the operand (a, b, etc.) would take five bits. This allows for eight opcodes and 32 addresses (this is a very basic microprocessor). Hence, we might find that the instructions translate as follows:

LOAD b 00000001 ADD c 01000010 STORE a 00100011

i.e. LOAD, ADD and STORE translate to 000, 010 and 001, respectively, while a, b and c are data at addresses 00011, 00001 and 00010, respectively.

Within the microprocessor there is the datapath/controller partition described in the last section. The controller (often known as a sequencer in this context) is a state machine. In the simplest case, the bits of the opcode part of the instruction are inputs to the controller, in the same way that A and X0are inputs to the controller of Figure 7.8. Alternatively, the opcode may be decoded (using a decoder implemented in ROM) to generate a larger set of inputs to the controller. The decoder pattern stored in the ROM is known as microcode.

The instructions shown above consist of an opcode and an address. The data to be operated upon must be subsequently obtained from the memory addresses given in the instruction. This is known as direct addressing. Other addressing modes are possible.

Suppose we wish to compile a = b + 5;

This translates to:

LOAD b ADD 5 STORE a

How do we know that the 5 in the ADD instruction means the value ‘5’ and not the data stored at address 5? In assembler language, we would normally use a special notation, e.g. ‘ADD #5’, where the ‘#’ indicates to the assembler that the following value is to be interpreted as a value and not as an address. This form of addressing is known as immediate mode addressing.

When the microprocessor executes an immediate mode instruction, different parts of the datapath are used compared with those activated by a direct mode instruction.

Hence the controller goes through a different sequence of states, and thus the opcodes for an immediate mode ADD and a direct mode ADD must be different. In other words, from the point of view of the microprocessor, instructions with different addressing modes are treated as totally distinct instructions and have different opcodes.