Resultados de la regulación vigente

Using the idea of partitioning a design into a controller and datapath, we will now show how a very basic microprocessor can be designed. We want to be able to execute simple direct mode instructions such as those described in the previous section. Let us first

164 Complex sequential systems

Figure 7.10 Datapath of CPU.

Sequencer

MDR MAR

RAM ACC

Flags ALU

PC IR

Control signals

consider the components of the datapath that we need. In order to simplify the routing of data around the microprocessor, we will assume the existence of a single bus. More advanced designs would have two or three buses, but one bus is sufficient for our needs.

For simplicity we shall assume that the bus and all the datapath components are eight bits wide, although we shall make the VHDL model, in the next section, parameterizable.

Because the single bus may be driven by a number of different components, each of those components will use three-state buffers to ensure that only one component is attempting to put valid data on the bus at a time. We will keep the design fully synchronous, with a single clock driving all sequential blocks. We will also include a single asynchronous reset to initialize all sequential blocks. A block diagram of the microprocessor is shown in Figure 7.10.

The program to be executed by the microprocessor will be held in memory together with any data. Memory such as SRAM is commonly asynchronous, therefore synchronous registers will be included as buffers between the memory and the bus for both the address and data signals. These registers are the Memory Address Register (MAR) and Memory Data Register (MDR).

The Arithmetic and Logic Unit (ALU) performs the arithmetic operations (e.g. ADD).

The ALU is a combinational block. The result of an arithmetic operation is held in a register, called the Accumulator (ACC). The inputs to the ALU are the bus and the ACC.

The ALU may also have further outputs, or flags, to indicate that the result in the ACC has a particular characteristic, such as being negative. These flags act as inputs to the sequencer.

The various instructions of a program are held sequentially in memory. Therefore the address of the next instruction to be executed needs to be stored. This is done using the Program Counter (PC), which also includes the necessary logic to automatically increment the address held in the PC. If a branch is executed, the program executes out of sequence, so it must also be possible to load a new address into the PC.

Finally, an instruction taken from the memory needs to be stored and acted upon.

The Instruction Register (IR) holds the current instruction. The bits corresponding

A simple microprocessor 165

Table 7.1 Control signals of microprocessor.

ACC_bus Drive bus with contents of ACC (enable three-state output) load_ACC Load ACC from bus

PC_bus Drive bus with contents of PC load_IR Load IR from bus

load_MAR Load MAR from bus

MDR_bus Drive bus with contents of MDR load_MDR Load MDR from bus

ALU_ACC Load ACC with result from ALU INC_PC Increment PC and save the result in PC

Addr_bus Drive bus with operand part of instruction held in IR CS Chip Select. Use contents of MAR to set up memory address R_NW Read, Not Write. When false, contents of MDR are stored in memory ALU_add Perform an add operation in the ALU

ALU_sub Perform a subtract operation in the ALU

to the opcode are inputs to the sequencer, which is the state machine controlling the overall functioning of the microprocessor.

The sequencer generates a number of control signals. These determine which components can write to the bus, which registers are loaded from the bus and which ALU operations are performed. The control signals for this microprocessor are listed in Table 7.1.

Figure 7.11 shows the ASM chart of the microprocessor sequencer. Six clock cycles are required to complete each instruction. The execution cycle can be divided into two parts: the fetch phase and the execute phase. In the first state of the fetch phase, s0, the contents of the PC are loaded, via the bus, into MAR. At the same time the address in the PC is incremented by 1. In state s1, the CS and R_NW signals are both asserted to read into MDR the contents of the memory at the address given by MAR. In state s2, the contents of MDR are transferred to IR via the bus.

In the execute phase, the instruction, now held in IR, is interpreted and executed. In state s3, the address part of the instruction, the operand, is copied back to MAR, in anticipation of using it to load or store further data. If the opcode held in IR is STORE, control passes through s4 and s5, in which the contents of ACC are transferred to MDR, then to be written into memory (at the address previously stored in MAR) when CS is asserted. If the opcode is not STORE, CS and R_NW are asserted in state s6, to read data from memory into MDR. If the opcode is LOAD, the contents of MDR are trans-ferred to ACC in state s7, otherwise an arithmetic operation is performed by the ALU using the data in ACC and in MDR in state s8. The results of this operation are stored in ACC.

The ASM chart of Figure 7.11 shows register transfer operations. In Figure 7.12, the ASM chart shows instead the control signals that are asserted in each state. Either form is valid, although that of Figure 7.11 is more abstract.

166 Complex sequential systems

Figure 7.11 ASM chart of microprocessor.

CS R_NW

IR MDR MAR PC PC PC+1

MAR Addr

MDR ACC CS

R_NW

s4 s6

op=store

1 0

s0

s1

s2

s3

ACC MDR

s8 op=load

1 0

CS s5

s7

op=add

1 0

ACC MDR +ACC

ACC MDR –ACC

ExecuteFetch

This processor does not include branching. Hence, it is of little use for running programs. Let us extend the microprocessor to include a branch if the result of an arithmetic operation (stored in ACC) is not zero (BNE). The ALU has a zero flag which is true if the result it calculates is zero and which is an input to the sequencer.

Here, we shall implement this branch instruction in a somewhat unusual manner.

All the instructions in this example are direct mode instructions. To implement immediate mode instructions would require significant alteration of the ASM chart.

Therefore we will implement a ‘direct mode branch’. The operand of a BNE instruc-tion is not the address to which the microprocessor will branch (if the zero flag is true), but the address at which this destination address is stored. Figure 7.13 shows how the lower right corner of the ASM chart can be modified to include this branch. An additional control signal has to be included: load_PC, to load the PC from the bus.

VHDL model of a simple microprocessor 167

Figure 7.12 Alternative form of microprocessor ASM chart.