Requerimientos y requisitos técnicos - metodológicos para la efectividad del

The charge readout front-end for MSDD sensors, presented in more detail in section 4.2.1, uses a PMOS input stage with a resistor at the drain node for signal compression. The input node con- nected to the MOS gate is left floating after reset. The input capacitance is especially important for the circuit, as the signal magnitude is given by the charge generated in the sensor volume creating a voltage step on the input capacitance.

The input capacitance of the F1 front-end has been determined by using the MIM capacitors, which can be connected to the input node, as a reference. By measuring the gain reduction after connecting a capacitor of known design value, the original capacitance can be calculated [44]. On the naked F1 measured on the probestation, the input capacitance of the 4k pixels has been measured to 896± 70 fF. After bump-bonding to an MSDD sensor, only a slight increase of 70 fF is expected due to the small contribution of the anode, in agreement with data from smaller test chips. The expected value from front-end design is much smaller at 400 - 500 f F. The additional capacitance is related to the DEPFET cascode PMOS which is also connected to the input node, with the n-well also being unnecesarily connected to the input node.

On a smaller test chip MM6, where the pixel only includes a MSDD front-end and no DEPFET cascode, a smaller input capacitance of 250 f F has been measured. Moreover, the bump landing pad size has been reduced here to reduce the capacitance. The given data will be used in a future full size chip to improve the input capacitance.

Measurements on single pixels

By means of the internal charge injection readily available in each pixel, the proper behaviour and operating conditions of a single channel have been evaluated before going to a larger set of pixels. A check of performance boundaries regarding gain and the achievable dynamic range will be shown here. The magnitude of the front-end’s response to a change on the gate node is the main point of interest here.

The bias point, in this case the voltage at the input node at the start of each cycle and thus the current in the input branch, is set by the periphery DAC. Its output voltage is distributed to every pixel through the Monitor Bus and is buffered by a source follower. By changing the periphery DAC setting, the start of the characteristic can be moved. Through the in-pixel injection circuit, a charge can be injected at the input node. This is shown in figure 6.15 for a set of periphery DAC settings, while the extracted gain in the first part is shown on the right. Here, the optimum reset voltage is 750 mV - small signal charges are amplified with maximum gain. The gain decreases for higher amounts of charge, in other words, compresses larger numbers of photons.

Using the design values for all involved components, the gmat the point of maximum gain can be estimated:

gm,max = ∆Ids ∆Vg =

nbinsVbinCftint

Vg (6.4)

The estimated value of≈ 1.3 mS is slightly larger than values from simulations. Deviations apart from component values might be caused from the uncalibrated magnitude of charge injected by the internal injection circuit.

A first glance at the maximum signal detectable by the front-end shows that after 150 injection steps (corresponding to≈ 2300 keV) the front-end saturates when starting at the maximum gain point. However, this dynamic range is only reachable for settings with relatively low gain at the

6.1 Full format ASIC F1

Figure 6.15: Single pixel measurement of the MSDD front-end response. Top: Pixel output as a function of the injected charge at the input, given as the digital value for the injection DAC (parameter: reset voltage). Bottom: The gain in the first part is a function of the reset voltage and the in-pixel VDDA.

beginning of the characteristic. The compression sets in very late, in this case, the first 70 injection steps (1000 keV) are basically uncompressed, filling 130 ADC bins. The following 1300 keV are compressed into the next 30 ADC bins. Of course, the front-end gain and ADC settings are in this case not optimized to use the full range of 256 bins, but the measurement already shows that the compression region is very small. More cases will be discussed in the next chapter.

The mean input capacitance has been measured to 0.9 pF. Additionally, extra capacitors (0.2 pF, 0.5 pF and 1.0 pF) can be added to the input, which reduces the voltage step on the input for a given input charge and thus increases the dynamic range of the circuit. The three capacitors result in seven possible combinations with a gain reduction between 22 % and 189 %.

The noise and further parameters of the circuit have been estimated with sensors and is given in chapter section 7.1.

Full matrix measurements

Figure 6.16: Gain of the first part of the characteristic, measured with all pixels running, for de- creasing bias voltages. The maximum gain is reached first in the lower left, where the analog supply is highest. By further decreasing the bias, the maximum gain shifts to the upper right part with lower VDDA.

The simple design of the MSDD input stage with the transistor’s source connected to VDDA performs well on single-pixel level, but more serious problems arise on matrix level. Since VDDA is not homogenous throughout the pixel matrix, the important front-end gain for the first photons is depending on the local VDDA inside the pixel, and therefore on parameters like the pixel position and number of active pixels. Figure 6.16 illustrates this by a map of the front-end gains of the first part while all pixels are active, with histograms attached, for a set of bias settings. For each pixel, the gain has been determined by means of the internal charge injection. In order to minimize crosstalk effects while keeping the measurement time at a reasonable level, sets of 128 pixels have been measured in parallel. From left to right, the bias voltage has been decreased. The ADC gains have been trimmed for this measurement to only see front-end variations in this measurement.

6.1 Full format ASIC F1

In the left plot at a reset voltage of 783 mV, the gain is well below the maximum, with a distribution similar to that of VDDA, with minima in the upper left and upper right parts (section 6.1.3). With decreasing bias voltage, the gain of all pixels increase, with a maximum at the lower left (center plot, reset voltage 728 mV) - the pixels here have the highest VDDA, the maximum gain is reached here first. Consequently, the gain in the lower left drops for further decreasing bias voltage, and the pixels across the center of the matrix reach the maximum gain (right, 673 mV). The mean gain across the matrix increases from 1.08± 0.23 ADU/Injection step (left plot) to 2.34 ± 0.28 ADU/Injection step (right plot). Tests have validated that the remaining gain deviations can be compensated by changing the filter’s feedback capacitor and IRmpcurrent pixel-wise.