• Spartan-3 CD de Recursos - Una recopilación de documentación útil
sobre el Spartan-3 familia, incluyendo notas de aplicación, hojas de
datos, diseños de referencia y los esquemas.
• JTAG Cable - Fácil de descargar un diseño a la FPGA desde el PC
puerto paralelo.
• Power Supply - fuente de alimentación universal (110-220 V, 50/60
Hz) proporciona una salida de +5 V a bordo de regulación de voltaje a
3,3 V, 2,5 V y 1,2 V.
• Guía - Detalles de Xilinx FPGA y los dispositivos de lógica programable
CPLD.
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APÉNDICE B
PROGRAMAS GENERADOS EN VHDL
MODULADOR BPSK:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package conv_pkg isconstant simulating : boolean := false -- synopsys translate_off
or true
-- synopsys translate_on ;
constant xlUnsigned : integer := 1; constant xlSigned : integer := 2; constant xlWrap : integer := 1; constant xlSaturate : integer := 2; constant xlTruncate : integer := 1; constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3; constant xlAddMode : integer := 1; constant xlSubMode : integer := 2; attribute black_box : boolean; attribute syn_black_box : boolean; attribute fpga_dont_touch: string; attribute box_type : string; attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; function std_logic_vector_to_signed(inp : std_logic_vector) return signed; function signed_to_std_logic_vector(inp : signed) return std_logic_vector; function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean; function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean; function is_point_five(inp: std_logic_vector) return boolean; function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER) return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector;
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return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed;
function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed;
function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector; function max_signed(width : INTEGER) return std_logic_vector; function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith, new_width: INTEGER)
return std_logic_vector;
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return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer) return std_logic_vector;
function max(L, R: INTEGER) return INTEGER; function min(L, R: INTEGER) return INTEGER; function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer) return signed;
function boolean_to_unsigned (inp : boolean; width: integer) return unsigned;
function boolean_to_vector (inp : boolean) return std_logic_vector;
function std_logic_to_vector (inp : std_logic) return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer) return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) return integer;
function std_logic_to_integer(constant inp : std_logic := '0') return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string) return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer) return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING; function and_reduce(inp: std_logic_vector) return std_logic; -- synopsys translate_off
function is_binary_string_invalid (inp : string) return boolean;
function is_binary_string_undefined (inp : string) return boolean;
function is_XorU(inp : std_logic_vector) return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) return std_logic_vector;
constant display_precision : integer := 20; function real_to_string (inp : real) return string; function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
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return string;
type stdlogic_to_char_t is array(std_logic) of character; constant to_char : stdlogic_to_char_t := (
'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'); -- synopsys translate_on end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned
is begin
return unsigned (inp); end;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector
is begin
return std_logic_vector(inp); end;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed
is begin
return signed (inp); end;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector
is begin
return std_logic_vector(inp); end;
function unsigned_to_signed (inp : unsigned) return signed
is begin
return signed(std_logic_vector(inp)); end;
function signed_to_unsigned (inp : signed) return unsigned
is begin
return unsigned(std_logic_vector(inp)); end;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean
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is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0); begin
vec := inp;
if arith = xlUnsigned then return true; else if vec(width-1) = '0' then return true; else return false; end if; end if; return true; end;
function max_signed(width : INTEGER) return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin
ones := (others => '1'); result(width-1) := '0';
result(width-2 downto 0) := ones; return result;
end;
function min_signed(width : INTEGER) return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0); variable result : std_logic_vector(width-1 downto 0); begin
zeros := (others => '0'); result(width-1) := '1';
result(width-2 downto 0) := zeros; return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0); begin
vec := inp; result := vec(0); if width > 1 then
for i in 1 to width-1 loop result := result and vec(i); end loop;
end if;
return result; end;
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function all_same(inp: std_logic_vector) return boolean is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0); begin
vec := inp; result := true; if width > 0 then
for i in 1 to width-1 loop if vec(i) /= vec(0) then result := false; end if; end loop; end if; return result; end;
function all_zeros(inp: std_logic_vector) return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0); variable zero : std_logic_vector(width-1 downto 0); variable result : boolean;
begin zero := (others => '0'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then result := true; else result := false; end if; return result; end;
function is_point_five(inp: std_logic_vector) return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0); variable result : boolean;
begin vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on
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if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then result := true; else result := false; end if; else if (vec(width-1) = '1') then result := true; else result := false; end if; end if; return result; end;
function all_ones(inp: std_logic_vector) return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0); variable one : std_logic_vector(width-1 downto 0); variable result : boolean;
begin one := (others => '1'); vec := inp; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then result := true; else result := false; end if; return result; end;
function full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER) return integer
is
variable result : integer; begin
result := old_width + 2; return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return integer
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variable right_of_dp, left_of_dp, result : integer; begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result; end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER) return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith); constant fp_bin_pt : integer := old_bin_pt; constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0); constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt; constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith); else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith);
end if;
return result; end;
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function cast (inp : std_logic_vector; old_bin_pt, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt) - (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then result(i) := '0'; else result(i) := vec(old_width-1); end if; elsif ( j >= 0) then result(i) := vec(j); else result(i) := '0'; end if; end loop; return result; end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) return std_logic_vector
is begin
return inp(upper downto lower); end;
function s2u_slice (inp : signed; upper, lower : INTEGER) return unsigned
is begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER) return unsigned
is begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) return signed
is begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
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end;
function s2u_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return unsigned is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER)
return unsigned is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width, new_bin_pt : INTEGER)
return std_logic_vector is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return std_logic_vector is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); end;
function boolean_to_signed (inp : boolean; width : integer) return signed
is
variable result : signed(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end;
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function boolean_to_unsigned (inp : boolean; width : integer) return unsigned
is
variable result : unsigned(width - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end;
function boolean_to_vector (inp : boolean) return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0); begin result := (others => '0'); if inp then result(0) := '1'; else result(0) := '0'; end if; return result; end;
function std_logic_to_vector (inp : std_logic) return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0); begin
result(0) := inp; return result; end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt); variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width);
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else
result := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if;
end if;
return result; end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if; else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else
truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if;
end if;
one_or_zero := (others => '0'); if (new_arith = xlSigned) then if (vec(old_width-1) = '0') then one_or_zero(0) := '1'; end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then one_or_zero(0) := '1';
end if; end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0'; end if;
else
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end if; else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then one_or_zero(0) := vec(right_of_dp-1);
end if; end if;
if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1; variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0); variable truncated_val : std_logic_vector(new_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if; else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); else
truncated_val := sign_ext(pad_LSB(vec, old_width + abs(right_of_dp)), new_width); end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then one_or_zero(0) := vec(right_of_dp-1);
else
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end if; end if;
if new_arith = xlSigned then result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + std_logic_vector_to_signed(one_or_zero)); else result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + std_logic_vector_to_unsigned(one_or_zero)); end if; return result; end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector is
constant left_of_dp : integer := (old_width - old_bin_pt) - (new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable overflow : boolean;
begin
vec := inp; overflow := true;
result := (others => '0');
if (new_width >= old_width) then overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then overflow := false;
end if; end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then overflow := false;
end if; else
if (old_width = new_width) then if (vec(new_width-1) = '0') then overflow := false; end if; end if; end if; end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then overflow := false;
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end if; else
if (old_width = new_width) then overflow := false;
end if; end if; end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then overflow := false;
end if; end if;
if overflow then
if new_arith = xlSigned then if vec(old_width-1) = '0' then result := max_signed(new_width); else result := min_signed(new_width); end if; else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then result := (others => '0'); else result := (others => '1'); end if; end if; else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then if (vec(old_width-1) = '1') then
vec := (others => '0'); end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0); else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width); else
result := sign_ext(vec, new_width); end if;
end if; end if;
return result; end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, old_arith, new_width, new_bin_pt, new_arith : INTEGER) return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0); variable result_arith : integer;
begin
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result_arith := xlSigned; end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is begin
return max(a_bin_pt, b_bin_pt); end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt); end;
function pad_LSB(inp : std_logic_vector; new_width: integer) return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1; begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then for i in orig_width-1 downto 0 loop result(pos) := vec(i);
pos := pos - 1; end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop result(i) := '0'; end loop; end if; end if; return result; end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop result(i) := vec(old_width-1);
end loop; end if;
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else
result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if;
return result; end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER) return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec; if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop result(i) := '0';
end loop; end if; else
result(new_width-1 downto 0) := vec(new_width-1 downto 0); end if;
return result; end;
function zero_ext(inp : std_logic; new_width : INTEGER) return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0); begin
result(0) := inp;
for i in new_width-1 downto 1 loop result(i) := '0';
end loop; return result; end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0); variable result : std_logic_vector(new_width-1 downto 0); begin
vec := inp;
if arith = xlUnsigned then