Análisis predictivo

Of course, the frequency response of the entire power delivery network is what is important. The system power supply must look low impedance at all frequencies of interest. Figure 6.16 shows how the ac impedance will vary as a function of frequency for a simple power delivery system. Bode plot techniques were used to estimate the impedance as a function of

frequency for the power delivery system. Note that the power delivery inductance, Lpwr, plays

a significant role in the frequency response. In this analysis, the effect of the series

resistance (ESR) was ignored. Another effect that is ignored in this analysis is the possibility of resonant poles that can significantly increase the impedance of the power delivery system. These resonant poles are covered briefly in Section 10.3.1.

6.3. SSO/SSN

Simultaneous switching output noise (SSO), which is sometimes referred to as simultaneous

switching noise (SSN) or delta-I noise, is inductive noise caused by several outputs

switching at the same time. For example, a signal switching by itself may have perfect signal integrity. However, when all the signals in a bus are switching simultaneously, noise

generated from the other signals can corrupt the signal quality of the target net. SSN is typically very difficult to quantify because it depends heavily on the physical geometry of the system. The basic mechanism, however, is the familiar equation

(6.11)

where VSSN is the simultaneous switching noise, N the number of drivers switching, Ltot the

equivalent inductance in which current must pass, and I the current per driver. When a large number of signals switch at the same time, the power supply must deliver enough current to satisfy the sudden demand. Since the current must pass through an inductance, Ltot, a noise

of VSSN will be introduced onto the power supply, which in turn will manifest itself at the driver

output.

SSN can occur at both the chip level and the board level. At the chip level, the power supply is not perfect. Any sudden demand for current must be supplied by the board-level power though the inductive chip package and lead frame (or whatever the connecting mechanism happens to be). On the board level, sudden current demands must be supplied through inductive connectors. As discussed in Chapter 5, any current flowing through a connector must be supplied and return through the power and ground pins, which will induce noise into the system. Furthermore, as discussed in Section 6.1, a nonideal return path will also cause an effective increase in the series inductance in the vicinity of the discontinuity. Furthermore, if the return path discontinuity forces the return current from several outputs to flow through a small area, SSN will be even more exacerbated.

Many of the mechanisms that contribute to SSN were discussed in Sections 6.1, 6.2, and 5.2.4. The area that needs further explanation is the chip/package-level SSN. To explain how SSN will affect signals on the chip, refer to Figure 6.17. The inductors represent the equivalent inductance seen at the power connections and the output of each I/O. As drivers 1, 3, and 4 switch simultaneously, several inductive noises will be generated. First, as the transient current flows through the power supply inductors, di/dt noise will be generated. This noise will be coupled to the power connections of quiet nets. It is possible for the power supply to get so noisy that it causes core logic to flip state. In another failing case, the input of a strobe or a clock receives enough noise that exceeds its threshold voltage, causing a false trigger. SSN will also distort the signal integrity, which can cause gate delays, which will sometimes be manifested as shown in Figure 6.12.

Figure 6.17: Simultaneous switching noise mechanisms.

SSN can be a very elusive noise to characterize. There are not many methods for quick approximations to get an easy assessment of SSN. Only careful examination of your package and power delivery system and detailed simulations can lead to a reasonable assessment of the magnitude of SSN. Even when attempts are made to characterize the noise accurately, it is almost impossible to determine an exact answer because the variables are so numerous and the geometries that must be assessed are three-dimensional in nature and depend heavily on the individual chip package (or connector) and the pin-out. Because of the difficulty of this problem, it is recommended that SSN be evaluated using both simulation and measurements. Subsequently, only general rules can be used to control this noise source.

Figure 6.18 is a generic model that can be used to evaluate SSN in a CMOS bus. The capacitors, CI/O, are the inherent on-die capacitance for each I/O cell. Lchip represents any

inductance seen on the chip between the CMOS gate and the power bus. Lpwr bus represents

the inductance of the power distribution on the die and package. Lgnd bus represents the

inductance of the ground distribution on the die and on the package. and Lgnd pin

represent the inductance of the power and ground pins on the package. LPCB plane represents

the inductive path between the pin and the nearest decoupling capacitor. Lcap represents the

series inductance of the decoupling capacitors, and represents the board-level

decoupling capacitors. Finally, Lout represents the series inductance of the package seen at

the I/O outputs. It should be noted that all mutual inductance values should be included in this model. Furthermore, the number of gates simulated should be equal to the number of gates that share the same power and ground pins.

Figure 6.18: Model used to evaluate component level SSN/SSO for a CMOS-driven bus.

Connector SSN is simulated as described in Section 5.2.4. It is important, however, that the decoupling capacitors and the inductive path to the capacitors be accounted for properly. If the general guidelines for connector design described in Section 5.2.6 are adhered to, connector-related SSN will be minimized. Nonideal return paths cause board-level SSN, which effectively increases the series inductance of the net. Subsequently, the avoidance of any nonideal return paths is critical. If a nonideal return path is unavoidable, the board must be heavily decoupled in the area of the discontinuity.