Análisis predictivo OTV-818-OE03 (02-03-2015), Termografía inyectores

The basic CMOS output buffer is shown in Figure 7.2. When the input is high, the output is driven low through the N-type device. When the input is low, the output is driven high through the P-type device. Conceptually, driving devices have been implicitly modeled elsewhere in this book, as shown in Figure 7.3. The impedance of the CMOS buffer shown in Figure 7.2 is dependent on the instantaneous operating conditions of the device. In other words, the impedance is dynamic. The instantaneous output impedance can be thought of as the slope (or the inverse slope) of the current—voltage (I-V) characteristic curve of the buffer. Some general curves for N and P devices are shown in Figure 7.4. The reader will recall the equations governing operation of the CMOS FET transistors as shown in

equations (7.1) through (7.4) [Sedra and Smith 1991]. The two regions of operation of a FET are the triode region and the saturation region. An N device is in the triode region if vds ≤ vgs

- Vt and in the saturation region if vds ≥ vgs - Vt, where Vt is the threshold voltage of the

device. A P device is in the triode region if vds ≥ vgs - Vt and the saturation region if vds ≤ vgs

- Vt.

Figure 7.3: General method of describing buffers elsewhere in this book.

Figure 7.4: NMOS and PMOS I-V curves.

For the triode region (see Figure 7.4), (7.1)

For CMOS devices, K is µCox(W/L), where µ is the mobility of charge carriers (i.e.,

electrons or holes) in the silicon, Cox the oxide capacitance, and W and L the width and

length of the transistor being considered. For the saturation region (see Figure 7.4), (7.2)

where is a positive parameter that accounts for the nonzero slope (i.e., the output impedance) of the curve in the saturation region. The output impedance in the saturation region is defined as

(7.3)

This is not the output impedance that should be considered in a model for the basic CMOS buffer, since the CMOS buffer is typically not operated in the saturation region. The output impedance in the saturation region is mentioned here only for completeness and later relevance. Zout in the saturation region is typically very high, and thus 0 is usually

assumed resulting in (7.4)

for the saturation region.

In order to derive models, let us briefly describe the operation of the basic CMOS buffer. Consider Figure 7.5, which shows the input to the buffer transitioning from low to high with an initial condition of Vdd volts at the output of the buffer. Vdd will be present at the gate of

both the P and N devices; thus the N device will have a gate-to-source voltage, Vgs, of Vdd.

The N device will thus be in an "on" condition and will begin to discharge the load to ground. Subsequently, this transition is often called the pull-down. The initial point (t = 0) on the transistor curve can be found on the Vgs = Vdd curve at Vds = Vdd, as shown in Figure 7.6a. At

time t = 0, the device operating point will be as shown and the N device will conduct current to discharge the load. As the load is discharged, Vds will decrease and the operating point

will shift downward on the curve until the load is discharged to very close to zero volts. The curve for the P device is also shown with Vgs = 0 V. The current conducted by the P device

at Vgs = 0 will be equal or very close to zero. The intersection of the P and N curve will be the

Figure 7.6: Operation of the CMOS output buffer when the input voltage is (a) high and

(b) low.

Conversely, when the input to the buffer transitions to zero volts, the N device will turn off and the P device will turn on, which will charge the load to Vdd. This is known as the pull-up

transition. The transistor curves shown in Figure 7.6b shows the steady-state output value of the buffer when the input is low. The impedance at any point along the discharge is the inverse of the slope of the I-V curve. In Figure 7.6a, the impedance varies widely, from a very high value at t = 0 to a lower value as the load discharges. This wide variation in impedance is, of course, not optimal if a controlled range of impedance is desired from the buffer for matching to a transmission line. Ideally, for precisely controlled impedance, the I-V curve will be that of a fixed resistor, which is a straight line, as shown in Figure 7.7.

Figure 7.7: Ideal I-V curve with a fixed impedance.

Recall that the impedance in the saturation region is very high; thus, operation in this region should be avoided when matched impedance is required. If the buffer is designed for operation primarily within the triode region, the impedance will vary much less, as shown in Figure 7.8. Generally, highly linear behavior of the buffer is a desired feature. In early stages of design, when actual buffer curves have not yet been defined, a linear model of the buffer can be used. The information gained from this model can be simulated with a larger system and help in defining the characteristics of the buffer-to-be. In the next section we detail the linear approximation of a buffer.

Figure 7.8: Different regions of the I-V curve exhibit different impedance values.

Let us consider the effect on total impedance of the series resistor (either integrated or discrete) as shown in Figure 7.1. The variation (with process, temperature, etc.) of the I-V curve of the transistor will vary. This will, of course, affect the impedance. Figure 7.9 shows three curves for a transistor at a given Vgs. This variation should be accounted for. Good

estimates may be obtained from silicon designers as to the total variation of a given buffer type. Otherwise, assumptions can be made at this point and system simulations can be conducted to determine the allowable constraints. Constraints on the buffer curves for a given design may ultimately be derived from these simulations and communicated back to buffer designers as design rules.

Figure 7.9: Variations in the buffer impedance at a constant Vgs due to fabrication

variations and temperature.

To see the effect of a series resistor on the buffer, consider Figure 7.10, which shows an N device in series with the resistor. The conclusions derived here will obviously apply to a P device as well. For the total effect of the N device in series with the resistor, the constant impedance of the resistor

Figure 7.10: Buffer in series with a resistor.

must be added to the impedance of the transistor. Since impedance is the inverse of the slope of the transistor curve, the extra impedance of the resistor results in a reduction of the slope of the effective buffer curve, as shown in Figure 7.11. The larger the resistor, the higher the impedance of the buffer and the more linear the curve. For resistors that are large compared to the low-impedance portion of the transistor, the impedance will be dominated by the value of the resistor and the slope of the I-V curve will be approximately 1/R. Note that with any resistor in series with a buffer, the I-V curve will asymptote at the saturation current of the transistor, since in this condition the transistor is a very high impedance and will dominate the slope of the curve.

Figure 7.11: Effect of increasing the series resistor.