Capital natural y diagnóstico ambiental

In some cases, link redundancy is required in addition to the redundancy of core subsystems (see Figure 6.9). Especially across the backplane, link redundancy has its advantages because it alleviates the need for immediate removal of the node if the backplane has been damaged and an exchange of the node is not possible in a timely fashion. It must be said one more time that the backplane or midplane is passive. There must not be any active components on the backplane—not even electrolytic capacitors. Ceramic capacitors and resistors for line termination are the only allowed passive components on the backplane or midplane. All active compo-nents must be on the cards that plug into the backplane or midplane or other removable subsystems of the router.

Redundant links are fairly simple for parallel buses and any interconnect with a low symbol rate. In those cases, alignment and skew are under tight control, and it can be made sure that there is no more than a half-symbol time skew between the pairs of a redundant link. Alignment can be taken as a given in parallel buses with low symbol rates. As a result, a switchover becomes easy even if the links are not clocked by the same oscillator. However, this is not the case for modern routers anymore. Most modern routers deal with data rates that do not allow for traditional buses or low rate links to be deployed. Once High Speed Serial Links are used, the situation is not as simple anymore. Deskew and alignment must be guaranteed in such a way that all bits belonging to a logical link are aligned and free of skew. Additionally, the skew between any individual active line card and its hot standby counterpart should be close to zero, but at maximum one bit time. As a result, the links must be clocked from the same redundant oscillator, and their Clock and Data Recovery (CDR) units must be identical. As a result, only transceivers from the same manufacturer can be used for redundant pairs of links since every manufacturer has its own CDR design.

FIGURE 6.8 Non-redundant line card with redundant links.

conn

Line card specific logic (Framers, Network Processors, CAMs, …) XCVR

with redundant

Links conn

Data

Select active

standby

Independent of the specifics of the implementation of the transceiver and its CDR, it must be able to select an input channel for forwarding based on information it receives on a select signal. This requires the redundant transceivers to have the basic architecture shown in Figure 6.10.

It is important to understand that this is required for all lanes within a channel.

If this is necessary in an environment with HSSLs, the logic is within the trans-ceiver because the coding on the line requires the analog or mixed signal portion to respond to channel input, independent of whether it is considered active or hot standby.

Another issue that is different for HSSLs from traditional transceivers is the Bit Error Rate (BER). While HSSLs are probably much more robust than Low Voltage Differential Signaling (LVDS) or Low Voltage TTL (LVTTL)—the mere fact that these operate at significantly higher symbol rates and that they use 8B/10B coding means they can detect code violations and errors easier than older technologies—

bit errors must be expected. HSSLs will report errors from time to time, unlike LVDS transceivers. HSSLs are monitored and must have bit error counters to deter-mine the BER over the link. The OAM&P entity typically sets two thresholds. One threshold is used to detect decreasing line quality; the other is used to take the line out of service. So if an error occurs, the system requires the link to resynchronize and restart, but also to notify the OAM&P entity via whatever measure to report BER1. If it is below both thresholds, then the OAM&P entity stores it in a log file and continues to operate normally. If the BER1 threshold is exceeded, then the OAM&P entity will notify the NMC of a possible line down situation in the near future (known as predictive failure analysis, or PFA). If errors continue to occur then the BER2 threshold will be exceeded rather quickly. The system will take the line out of operation and will notify the operator about this issue. On a chip level, there must be the bit error counter and a possibility to generate an interrupt upon exceeding BER1 and BER2. (See Figure 6.11.)

FIGURE 6.9 Line or port card with redundant links.

conn

Line card specific

logic XCVR

with redundant

Links conn

FIGURE 6.10 Redundant transceiver, in a single lane or bit parallel.

FIGURE 6.11 Redundant switch fabric interface.

register bank or FIFO

register bank or FIFO

register bank or FIFO

to SF A

to SF B

from SF A

from SF B from NP

to NP

redundant Switch Fabric Interface with select and

auto-replication Switch Fabric Interface

The entire situation becomes a little bit more difficult in routers that must make use of parallel High Speed Serial Links. Not only are deskew and alignment between the individual lanes of a channel required to be monitored and kept under control;

more importantly, the redundant parallel HSSL must be aligned and synchronized during all times as well. The availability of the redundant parallel HSSL is key to the switchover and potential loss of data.