Dimensiones ejecutiva y legislativa

The Cell Delay Variation (CDV) is an ATM-only parameter. It pertains to ATM only because only ATM has a TDM-like traffic type, CBR (Constant Bit Rate), which is used for voice calls. Cell Delay Variation impacts voice calls and unencoded video

data only. MPEG-encoded video streams are practically not impacted by the CDV.

However, a large CDV will force a large packet delay variation, and for real-time video transmittals it will result in a larger delay between the data sent and the data displayed; as a consequence, it will require deeper buffers on the receiving side.

Large CDV will also require an echo cancellation circuit if the router is used to transport voice calls. A router designer should strive for a low packet delay and delay variation, and therefore typically will demand a low CDV from the switch fabric.

The important parameters for the minimum, maximum, and average CDV deter-mine the quality of the switch fabric.

SCALABILITY

Scalability is of foremost importance during the expected life cycle of a router or a switch. There are two major components to scalability. One is that the switch fabric is scalable, and the other is that the node must be able to make use of scaled-up switch fabric components without requiring a forklift upgrade. In order to be useful over the life of the node, the switch fabric, as the core component, must be scalable by architecture. This means that one generation of a switch fabric must span a wide range of port numbers and port speeds without performance bottlenecks while scaling up and without dramatic overprovisioning of performance during the first part of the cycle—and therefore without the additional cost associated with it. The line cards should be independent of the hardware specifics of the switch fabric and therefore independent of the total capacity. As an example, a node could be designed such that it supports a backplane with 16 slots, initially only supporting 8 line cards with 2.5 Gbit/s (OC-48) line cards, thus supporting a total of 20 Gbit/s full-duplex user traffic. This design might then require migration to a 16-port system with either the same cards, quad OC-48 cards, or 10 Gbit/s (either OC-192 or 10 GbE) ports, thus requiring a total switch fabric capacity of 40–160 Gbit/s full-duplex net user bandwidth. It is more than desirable if the line cards do not have to be changed if they are deployed in the larger system, and it is very helpful in terms of software development time if the 2.5 Gbit/s line cards are software-compatible with the 10 Gbit/s line cards. This would require that all switch fabric components are located on the switch fabric card. It also requires that there are switch fabric configurations that span a range from 20–160 Gbit/s net user bandwidth. Additionally, adding throughput should also add VOQs and scheduling performance, so that bottlenecks in scheduling can be avoided altogether if migrating to larger configurations.

The switch fabric partitioning must be such that an upgrade or update to any component leaves the other components unchanged. This is necessary to avoid forklift upgrades. For example, a higher-speed line card that gets swapped in for a lower-speed older line card should not necessitate a hardware change anywhere else.

Likewise, if the switch fabric capacity is increased, no line card should be affected.

This requires that all switch fabric components reside on the switch fabric card. A switch fabric component residing on a line card very likely is affected by a capacity upgrade—even if it is just the number of ports or the port speed, and thus the queue depth is increased. A switch fabric upgrade must not necessitate any hardware change to a line card. Also, for reliability reasons, all switch fabric components must be

covered by the 1:1 redundancy of the switch fabric card. That again requires these components to be assembled on one physical card. Components that are not on the switch fabric card but somewhere else cannot be included in the 1:1 redundancy, and therefore are not covered by the redundancy architecture. This dramatically decreases the system availability.

Scalability additionally means that the number of switch fabric ports can be increased without impacting the line cards that are already installed. This is espe-cially an issue in installations that will grow linearly over time.

Adding a line card means adding a port. If a switch fabric is capable of supporting N ports, then adding one port renders N + 1 ports that the upgraded switch fabric must be able to support. Usually, switch fabrics support 2ⁿ ports, and if N = 2ⁿ, then the entire switch fabric must be exchanged for a switch fabric with a larger capacity.

While this seems problematic, it is not really an issue. This is easily accomplished, especially in installations with redundant cards. The hot-standby card is placed into the status Maintenance Blocked (MBL), subsequently in Unavailable (UNA), and then removed. The new card with the higher capacity is installed and placed into the status MBL. After it is initialized, it can be put into the status Active (ACT), and the remaining card can be handled in a similar way. After everything is returned to ACT and Standby (STB), the system is extended in its switching capacity. That requires that the switch fabric cards contain all components, including the queue manager. If the queue manager is on the line cards, then the number of VOQs supported remains the same, even after upgrading the switch fabric card; therefore, the additional ports cannot be used since there is no VOQ for them. As a result, the router cannot be upgraded by just exchanging the switch fabric card. Instead, the line cards must be exchanged as well.

Scaling up the switch fabric is not a trivial issue. It certainly is limited by the implementation if the current architecture is kept. Die sizes are expected to be huge.

On the upside, however, another architecture that has chosen to go with queues at every crosspoint faces this problem to an even higher extent. With VOQ-based architectures, the memory required basically grows linearly with the number of ports N, and, to a lesser extent, with the port speeds. Queues at every crosspoint imply a growth according to N². It appears that the growth of single-stage routers is limited by the size of buffered and queued switch fabrics. There may be a shift in paradigm to deploy multistage switch fabrics in routers.

However, we can determine the degree to which scalability is possible in the current paradigm of VOQ or CVOQ switch fabrics. If we assume we will have to linearly increase single-stage switch fabric capacity, we can see the implications.

Let us assume that for the time being a net (payload) 5.12 Tbit/s switch is sufficient.

The challenge then is to find out which architecture to use. If VOQ architecture is deployed, then the individual queues impose a big implementation problem. At 10 Gbit/s a 1024 cell VOQ is acceptable to prevent Head-of-Line blocking. It is to be assumed that for a 40 Gbit/s solution, 4,096 cells are required to be stored per VOQ, and that number will have to increase if the network processor or the traffic manager has a proportionally higher latency at these speeds. So for a 40 Gbit/s port, every VOQ must be able to hold 4,096 cells. If the current function split is kept, then the queue manager must hold vastly more and faster memory than any current

one. It must hold a total of 4,096 cells per VOQ, multiplied by 64 or 128, depending on the internal datagram size. This is a total of 524,288 internal datagrams, or 37,748,736 bytes if 72 byte internal datagrams are used. It is a total of an impressive 301,989,888-bit (around 300 Mbit) SRAM only for the payload in the VOQ in the queue manager. Not only is this significantly more SRAM than deployed today, it also must run at higher speeds. Additionally, it does not yet incorporate any tags, transient LCIs, and Output Queues; nor does it include the logic for the schedulers.