DESARROLLO ADMINISTRATIVO.
3. Club con comisión técnica operando a Cumple completamente
Due to the charge transfer through the sensor, CCDs suffer from disadvantages. The distance for the transfer scales with the pixel size which is, therefore, not indefinitely scalable. The malfunction of one pixel can influence a complete detector row if charge carriers are trapped or generated at defects in the crystal structure. In addition, bright sources contaminate all pixel in the column parallel to the readout direction since the pixels are not blinded during the charge transfer. Such detections are called out-of-time events. To get a sufficient two- dimensional spatial resolution, the exposure time has to be much longer than the charge transfer through the whole sensor. To speed up the latter, some CCDs feature a blinded frame storage region to decouple the readout speed from the charge transfer. Such effects were overcome with the invention of active pixel sensors in 1985.[120] A readout node is implemented into each pixel. This also enables the implementation of further functionality into a pixel like a non-destructive readout. The amplification of the detection at this early stage improves the S/N and by using a built-in potential minimum, the pixel can be switched off completely during charge collection to safe power compared to the electrodes of a CCD. APSs replaced CCDs in commercial applications like digital and cell phone cameras and feature pixel sizes down to1×1 µm2.[108] An implementation of an APS for the usage in X- ray astronomy is the DEPFET which will be introduced in the next chapter. The significantly increased number of readout nodes with all its contacts that need to be attached to steering and readout lines, enforces a more complex wiring and electronics (see chapter 4). Depending on the readout mode, APSs cause different problems – compared to CCDs – as described in section 5.1. On top of that, a readout node inside the pixel also allows for the integration of functionality directly into the pixel. This opens up the possibility to address further issues that occur in applications which have to handle large intensity variations, a high throughput for bright sources, ultra low noise for small signals or an excellent time resolution.
Chapter 3
DEPFET Active Pixel Sensor
DEPFETs are one option to implement an active pixel sensor. The key idea is the amplification of the collected signal charges within the pixel and a readout that does not destruct the measured electrons. It allows for the implementation of further features like a shutter, a storage, or non-linear characteristics for a high dynamic range. The direct readout that does not need any charge transfer to the border of the sensor makes shorter frame times feasible compared to other imaging sensors.
The signal amplification and readout – the determination of the number of collected charges – is based on transistors. A transistor consists of three parts. The current between two of them – the source and the drain which act as source and sink for charge carriers – is controlled by the third one – the gate. Besides others, the MOSFET[a] is one implementation of a transistor. Its functionality was demonstrated in 1960.[95] A field-effect transistor (FET) is a transistor where only one type of charge carriers (electrons or holes) is involved. The gate of a MOSFET is composed of a metallic (M) contact insulated via an oxide (O) from the semiconductor (S) where the source and the drain regions are implemented. The name MOSFET is still in use although the conducting metal layer of the gate is usually replaced by poly-silicon. For a p-channel transistor, source and drain are implemented as p-doped regions in the slightly n-doped silicon wafer. At the edges of the implants, the p-n junction (section 2.4) establishes a depletion zone. A negative voltage at the gate contact repels the majority carriers (electrons) from the surface and forms a conductive channel between source and drain. The necessary minimum voltage between gate and source to establish an unintermittent channel is the threshold voltage Uth. In the formed channel the number of minority carriers is larger than the number of majority carriers. In semiconductors in general and in the transistor in particular, this state is called inversion (Fig. 3.1).
The relation between the change in the gate-source voltage UGS and the deviation of the transistor current IDS is called transconductancegm.
gm= ∂IDS
∂UGS (3.1)
Source Gate Drain Insulator -V p+ p+ n−
Figure 3.1:Transistor in inversion. The negative voltage at the gate contact repels the electrons of the donor atoms in the n-doped substrate under the oxide (insulator) and forms a conductive channel between source and drain that allows for a hole current between the two regions.
The transconductance can also be expressed with the potential difference between source and drainUDS or the current between the two regionsIDS, the capacity per unit area of the gate oxideCox= ox0/dox as well as the width W and the lengthL of the gate.[113]
gm=−W LµhCoxUDS = s −2W LµhCoxIDS (3.2)
3.1 DEPFET
The DEPFET is a p-channel MOSFET (PMOS) integrated on an fully depleted silicon bulk invented by Kemmer and Lutz (1987).[98] Compared to a simple MOSFET described above there are some further adaptations. A shallow p-implant under the gate with its dopant maximum a few tens of nanometre below the Si-SiO2 interface shifts the threshold voltage Uthto more positive values and the conductive channel deeper into the device.[200]It prevents charge carriers from interaction with defects at the Si-SiO2 interface. Such buried channels that were two orders of magnitude deeper in the silicon bulk, have already been used for CCDs to improve the CTE[b].[209] To form the DEPFET, a shallow deep n-implant is realised below the complete transistor structure. In the source and the drain regions this implant is partially compensated by the p-implants. This leads to the formation of a positive potential minimum for electrons below the external gate of the transistor (see Fig. 3.2). The electrostatic field generated by the electrons collected in the local minimum needs to be compensated by positive charges – holes – in the environment. Such so-called mirror charges arrange primarily in the transistor channel. These holes contribute to the charge drift in the transistor and therefore its conductivity. Since the collected electrons influence the properties of the transistor channel in a similar way as the MOSFET gate, it is called internal gate while
3.1 DEPFET 33 Source Gate Drain Internal gate p+ p + n− n−
Figure 3.2: Cross section through a DEPFET. The baseline for the charge collecting internal gate is a high energy arsenic or phosphorus implant (green). The large dose boron implant (red) that is shot after the second poly-silicon layer (dark grey) forms the drain, the source and, by omission, the internal gate that is located under the transistor gate. The electrons in the internal gate influence the conductivity of the transistor channel through mirror charges and are thereby measurable without destruction.
the gate is often termed external gate for a unique nomenclature. In the first order, the corresponding transconductance of the internal gate is given by[113]
gq= ∂IDS ∂Qsig ∝ − 1 L2µhUDS= s − 2µh W L3CoxIDS (3.3)
where Qsig is the collected signal charge. Since not all mirror charges are located within the transistor channel, the two sides of eq. (3.3) are only proportional to each other. The constant of proportionality is the fraction of collected electrons that generate a mirror charge in the conductive channel.
To be able to remove the collected electrons from the internal gate, n-channel transistors are situated at each gate. While the internal gate serves as source, the n+ implant is the drain. To minimise potential charge loss to this clear region during the charge collection, it is protected by a deep p-implant.
The baseline layout which is used on board of BepiColombo and that was the fallback option for the WFI of Athena is the so-called Cut Gate design as shown in Fig. 3.3a. The drain region in the centre is surrounded by a circular gate. The area around the gate is occupied by the source and, depending on the size of a pixel, one or more drift structures. On one side the external gate is truncated and the clear transistor is connected. Taking into account that misalignments in the manufacturing process may occur, the two poly-silicon layer that form the clear gate and the external gate overlap. The Cut Gate layout is minimised to essential parts that are necessary for a DEPFET, but has also some disadvantages. The contact hole and the corresponding steering line for the drain confine the minimum gate width while the contact hole for the gate limits its length. The maximum path that an electron has to drift through the internal gate to reach the clear transistor is roughly half the circumference of the gate. The lower limit for the gate width also sets a minimum for this maximal clear distance.
Source Drain Gate Internal gate @ @ @ I 6 Bulk Back side contact (a) Drain Source Ring Clear gate Clear (b)
Figure 3.3:A model of(a)a Cut Gate, the former baseline layout of a DEPFET for X-ray spectroscopy, and(b)a Linear Gate as it is planned for the Athena WFI. The electrons generated by an incident X-ray photon in the fully depleted silicon bulk are collected in the internal gate. By measuring the hole current between the drain and the source or the source voltage for a fixed current, the number of electrons in the internal gate can be determined. The collected charges can be removed through the clear transistor.
Since the electrostatic potential drops exponentially with the distance, this lower limit in the Cut Gate design is one of the biggest issues that affects the completeness of the clear process and thereby the spectroscopic performance due to the readout scheme presented in section 5.1.
The limitation of such a circular gate structure can be omitted by changing to a linear gate shape with two clear regions, each on one side of the DEPFET gate. Besides a larger clear area, further poly-silicon spacers are needed to separate source, drain and the drift rings. The layout for the steering lines and contacts becomes more challenging since external gate, clear gate and clear are aligned in one direction perpendicular to the source–drain orientation. Nevertheless, the large pixels of the Athena WFI set by the performance of the Athena optics allow for larger structures. In addition, by changing to shared contacts between the pixels, it is possible to build the tiniest DEPFETs currently available on the basis of linear gates (see section 7.1.2).[112]